Intel® FPGA SDK for OpenCL™ Pro Edition: Programming Guide

ID 683846
Date 6/21/2022
Public

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2.2. Multistep Intel® FPGA SDK for OpenCL™ Pro Edition Design Flow

Choose the multistep Intel® FPGA SDK for OpenCL™ Pro Edition design flow if you want to iterate on your OpenCL kernel design to implement optimizations or other iterative modifications.
Tip: If you are looking for or interested in learning about DPC++ FPGA design flows, refer to Types of DPC++ FPGA Compilation in the Intel® oneAPI Programming Guide.

The following figure outlines the stages in the SDK's design flow. The steps in the design flow serve as checkpoints for identifying functional errors and performance bottlenecks. They allow you to modify your OpenCL kernel code without performing a full compilation on each iteration. You have the option to perform some or all of the compilations steps.

Figure 5. Multistep Intel® FPGA SDK for OpenCL™ Pro Edition Design Flow

The SDK's design flow includes the following steps:

  1. Emulation

    Assess the functionality of your OpenCL kernel by executing it on one or multiple emulation devices on an x86-64 host system. For Linux systems, the Emulator offers symbolic debug support. Symbolic debug allows you to locate the origins of functional errors in your kernel code.

  2. Intermediate Compilation

    There are two available intermediate compilation steps. You have the option to include one or both of these compilation steps in your design flow.

    • Compile one or more .cl kernel source files using the -c flag. Doing so instructs the offline compiler to generate .aoco object files that contain the output from the OpenCL parser.
    • Compile one or more .cl kernel source files or .aoco files, but not both, using the -rtl flag. Doing so instructs the offline compiler to perform the following tasks:
      • If the input files are .cl files, the offline compiler generates an intermediate .aoco file for each kernel source file and then links them to generate a .aocr file.
      • If the input files are .aoco files, the offline compiler links them to generate a .aocr file.
      • Creates a <your_kernel_filename> directory.
      The offline compiler uses the .aocr file to generate the final .aocx hardware configuration file.
      Note: If you compile your kernel(s) using the -c flag in an environment where the default board is X, and then you compile your .aoco files using the -rtl flag in an environment where the default board is Y, the offline compiler reads board X from the .aoco files and then pass it on to the subsequent compilation stages.

  3. Review HTML Report

    Review the <your_kernel_filename>/reports/report.html file of your OpenCL application to determine whether the estimated kernel performance data is acceptable. The HTML report also provides suggestions on how you can modify your kernel to increase performance.

  4. Simulation (Preview)
    Assess the functionality of your OpenCL kernel by running it through simulation. Simulation lets you asses the function correctness and dynamic performance of your kernel without a long compilation time. You can capture and view waveforms for your kernel to help you debug your kernel.
    Note: The performance of the simulator is very slow when compared to that of hardware. So, Intel recommends using a smaller data set for testing.

  5. Fast Compilation
    Assess the functionality of your OpenCL kernel in hardware. The fast compilation step generates a .aocx file in a fraction of the time required to complete a full compilation. The Intel® FPGA SDK for OpenCL™ Offline Compiler reduces compilation time by performing only light optimizations.
    Note: Fast compilation allows you to compile quickly. However, the performance is inferior than a regular Intel® Quartus® Prime Pro Edition compilation.

  6. Incremental Compilation

    Assess the functionality of your OpenCL kernel in hardware. The incremental compilation step generates a .aocx file by compiling only the kernels you have modified. The Intel® FPGA SDK for OpenCL™ Offline Compiler improves your productivity by scaling compilation times with the size of your design changes rather than the size of your overall design.

  7. Profiling

    Instruct the Intel® FPGA SDK for OpenCL™ Offline Compiler to insert performance counters in the FPGA programming image. During execution, the counters collect performance information that you can then review in the Intel® FPGA dynamic profiler for OpenCL™ GUI.

  8. Full deployment

    When you are satisfied with the performance of your OpenCL kernel throughout the design flow, perform a full compilation. The resulting .aocx file is suitable for deployment.

For more information about the HTML report and kernel profiling, refer to the Intel® FPGA SDK for OpenCL™ Pro Edition Best Practices Guide.