2.4. Functional Description
You can use the design as an example for correct connection of your IP core to your design, or as a starter design you can customize for your own design requirements. The design example includes an I2C master module, a PLL/CDR recalibration module, one external transceiver PLL IP core, and logic to generate and check transactions. The design example assumes a Micron HMC 15G-SR HMC device, which is a four-link device, on the daughter card. The design example includes one instance of the IP core and connects to a single link on the HMC device.
After you configure the Arria 10 FPGA with the design example, the I2C controller configures the on-board clock generators and the HMC device. When calibration completes, the design example calibrates the ATX PLL. During operation, the request generator generates read and write commands that the HMC Controller IP core then processes. The request monitor captures the responses from the IP core and checks them for correctness.
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