Hybrid Memory Cube Controller Design Example User Guide

ID 683817
Date 5/02/2016
Public

1.2. Design Example Components

The HMC Controller hardware design example includes the following components:

  • HMC Controller IP core with CDR reference clock set to 125 MHz and with default RX mapping and TX mapping settings.
    Note: The design example requires these settings to operate properly on the Arria 10 GX FPGA Development Kit with the HMC daughter card.
  • Client logic that coordinates the programming of the IP core, and packet generation and checking.
  • JTAG controller that communicates with the Altera System Console. You communicate with the client logic through the System Console.
Figure 3. HMC Controller Design Example Block Diagram
Table 1.  HMC Controller IP Core Design Example Testbench File DescriptionsLists the key files that implement the example testbench.

File Names

Description

Testbench and Simulation Files

/src/hmcc_example.sv Top-level hardware design example file.
/sim/hmcc_tb.sv Top-level file for simulation.

Testbench Scripts

Note: Use the provided Makefile to generate these scripts.
/sim/run_vsim.do

The ModelSim script to run the testbench.

/sim/run_vcs.sh

The Synopsys VCS script to run the testbench.

/sim/run_ncsim.sh

The Cadence NCSim script to run the testbench.

Table 2.  HMCC Controller IP Core Hardware Design Example File Descriptions

File Names

Description

hmcc_example.qpf Intel® Quartus® Prime project file
hmcc_example.qsf Intel® Quartus® Prime project settings file
hmcc_example.sdc Intel® Quartus® Prime project Synopsys Design Constraints file
../src/hmcc_example.sv Top-level Verilog HDL design example file

Scripts

sysconsole_testbench.tcl

Main file for accessing System Console

Did you find the information on this page useful?

Characters remaining:

Feedback Message