AN 906: Intel® Stratix® 10 GX 400, SX 400, and TX 400 Routing and Designing Floorplan Guidelines

ID 683813
Date 2/06/2020
Public

1.1.3. Logic Utilization

With the preliminary internal investigations, Intel® recommends you to keep the logic utilization in your design below 70%. For designs with more than 70% logic utilization, there is a high risk that your design might not meet the timing requirements.

Initial analysis of push button performance is based on a design with the following logic utilization and clock frequencies.

Table 2.  Example Logic Utilization and Clock Frequencies
Clock Frequency (MHz) Logic Utilization
491 16%
368 25%
320 25%

Allow register transfer level (RTL) rewrite and pipelining to help meet timing requirements.

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