AN 906: Intel® Stratix® 10 GX 400, SX 400, and TX 400 Routing and Designing Floorplan Guidelines

ID 683813
Date 2/06/2020
Public HPS-to-Core and I/O-to-Core Traffic

Figure 4. HPS-to-Core and I/O-to-Core Traffic

The hard processor system (HPS)-to-core connectivity on the top-right corner along with the routing congestion in the area makes the I/Os in that bank not suitable for EMIF and LVDS interfaces. Connecting the core logic at the right of the HPS interface to any logic going out of the area will increase the chance of routing congestion.

Limit the logic in the area by using the Logic Lock feature on designs to allow enough routing usage to ease congestion. If additional latency is allowed, pipelining helps mitigating the issue.