AN 906: Intel® Stratix® 10 GX 400, SX 400, and TX 400 Routing and Designing Floorplan Guidelines

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ID 683813
Date 2/06/2020
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Document Table of Contents
Document Table of Contents x
1. AN 906: Intel® Stratix® 10 GX 400, SX 400, and TX 400 Routing and Designing Floorplan Guidelines
1. AN 906: Intel® Stratix® 10 GX 400, SX 400, and TX 400 Routing and Designing Floorplan Guidelines x
1.1. Device Area Constraints 1.2. Document Revision History for AN 906: Intel® Stratix® 10 GX 400, SX 400, and TX 400 Routing and Designing Floorplan Guidelines
1.1. Device Area Constraints x
1.1.1. Chip Layout 1.1.2. Floorplan Restrictions 1.1.3. Logic Utilization
1.1.2. Floorplan Restrictions x
1.1.2.1. Possible Congestion Areas 1.1.2.2. HPS-to-Core and I/O-to-Core Traffic 1.1.2.3. HPS Chimney 1.1.2.4. EMIF Usage
1.1.2.1. Possible Congestion Areas x
1.1.2.1.1. HPS and I/O Bank 3D Top-right Area 1.1.2.1.2. SDM and I/O Bank 3A Bottom-right Area
1. AN 906: Intel® Stratix® 10 GX 400, SX 400, and TX 400 Routing and Designing Floorplan Guidelines

1.1.2.2. HPS-to-Core and I/O-to-Core Traffic

Figure 4. HPS-to-Core and I/O-to-Core Traffic

The hard processor system (HPS)-to-core connectivity on the top-right corner along with the routing congestion in the area makes the I/Os in that bank not suitable for EMIF and LVDS interfaces. Connecting the core logic at the right of the HPS interface to any logic going out of the area will increase the chance of routing congestion.

Limit the logic in the area by using the Logic Lock feature on designs to allow enough routing usage to ease congestion. If additional latency is allowed, pipelining helps mitigating the issue.

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