AN 906: Intel® Stratix® 10 GX 400, SX 400, and TX 400 Routing and Designing Floorplan Guidelines

ID 683813
Date 2/06/2020
Public HPS and I/O Bank 3D Top-right Area

This is a place of possible congestion. Due to the fabric routing limitation, the external memory interface (EMIF) and LVDS on this side are not accessible.
Figure 2. HPS and I/O Bank 3D Top-right Possible Congestion Area Intel® recommends you to avoid the marked M20K line inside the area of emphasis to mitigate possible issues.