184.108.40.206. EMIF Usage
There is a risk of closing timing in the EMIF usage on banks 3B and 3C if the HPS and secure device manager (SDM) usage on top and bottom provides congestion in areas crossing the EMIF logic interfaces. Proper usage placement of EMIFs helps lessen the congestion.
You will be unable to access the EMIF usage on banks 3A and 3D due to a high risk of not being able to meet timing. Logic and memory resources available aggravated by routability issues at the right-bottom corner between the SDM and EMIF bank 3A and at the top-right corner between the HPS and EMIF bank 3D make it hard to meet timing closure.
|Bank||Intel® Stratix® 10 TX 400 (1ST040)||Intel® Stratix® 10 GX 400 (1SG040) and SX 400 (1SX040)|
|3A||Use for any general-purpose I/O (GPIO)||Use for GPIO only|
|3B||Use for GPIO, EMIF, or LVDS||Use for GPIO, EMIF, or LVDS|
|3C||Use for GPIO, EMIF, or LVDS||Use for 3.3V GPIOs only|
|3D||Use for any GPIO||Use for 1.8V GPIO only (it has 30 pins)|
Real-design experiments will determine if a combination of HPS, SDM, and EMIFs on the right column is feasible.
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