F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 4/03/2023
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design 7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Simulating the Design Example Testbench 1.4. Hardware and Software Requirements 1.5. Compiling and Configuring the Design Example in Hardware 1.6. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.7. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Two Separate Instances of IP Design 1.1.3. Generating Multiple IP Instance Design
1.3. Simulating the Design Example Testbench x
1.3.1. Fast Sim Model for FGT Variants 1.3.2. Fast Sim Model for FHT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design x
6.1. Features 6.2. Functional Description 6.3. Simulation 6.4. QSF Assignments 6.5. Hardware Design Example
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design
7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

6.3. Simulation

The testbench provides basic functionality such as the startup and waits for lock and send and receive a few packets using the ROM-based packet generator
Important: Before the simulation, you must generate tile-related files and specify the colocate assignment in the .qsf file to map both the instances of F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP to the F-Tile Ethernet Intel FPGA Hard IP for successful simulation as shown below.
Note:
  1. Append the eth_f_hw.qsf file as shown below:
    • Use the following syntax to colocate assignments:
      set_instance_assignment -name IP_COLOCATE \
-from <ANLT IP hierarchical path>  -to <Ethernet hierarchical path> <tile type>
    • Example:
      set_instance_assignment -name IP_COLOCATE \
-from ANLT IP INST0[0].kr_dut|eth_anlt_f_0 -to IP_INST[0].hw_ip_top|dut|eth_f_0 F_TILE
      set_instance_assignment -name IP_COLOCATE \
-from ANLT_IP_INST1[1].kr_dut|eth_anlt_f_0 -to IP_INST[0].hw_ip_top|dut|eth_f_0 F_TILE
  2. At the command prompt, navigate to the hardware_test_design folder in your example design:
    cd <your_design_path>/hardware_test_design
  3. Run the following command to generate eth_f_hw_tiles files:
    quartus_tlg eth_f_hw
  4. At the command prompt, change to the testbench simulation directory.
    CD <design_example_dir>/ex_*G/sim
  5. Run the IP setup simulation:
    ip-setup-simulation --quartus project=../../hardware_test_design/eth_f_hw.qpf
  6. Add the following macro to your simulation run script for AN/LT enabled designs:
    • For FGT
      +define+INTC_SIM_AN_LT_ENABLE
    • For FHT
      +define+RTL
    Note: In generated design example, the colocate assignments are already available in qsf file by default. Therefore, steps 1 to 5 can be skipped in the design example.
Figure 20.  F-Tile Ethernet Intel FPGA Hard IP Simulation Design Example Block Diagram with Enabled Auto-Negotiation and Link Training
The following steps show the simulation testbench flow:
  1. Assert global resets (i_rst_n and i_reconfig_rst) to reset the F-Tile Ethernet Intel FPGA Hard IP and F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IP.
  2. Wait until configuration settings load.
  3. Wait until resets acknowledgment. The o_rst_ack_n signal goes low.
  4. Deasserts the global resets, i_rst_n and i_reconfig_rst.
  5. Wait until auto-negotiation is complete. The data mode begins.
  6. Wait until link training is complete.
  7. Wait until o_tx_lanes_stable bit is set to 1, indicating TX path is ready.
  8. Wait until o_rx_pcs_ready bit is set to 1, indicating RX path is ready.
  9. Repeat steps 4 and 5 to complete the reset sequence for all the IP instances.
  10. Instruct packet client to transmit data. Write hw_pc_ctrl[0]=1'b1 to start the packet generator.
  11. Read TX packet data information from 0x20 - 0x34 registers. Read register in sequential order.
  12. Read RX packet data information from 0x38 - 0x4C registers. Read register in sequential order.
  13. Compare the counters to ensure 16 packets were sent and received.
  14. Instruct packet client to stop data transmission. Write hw_pc_ctrl[2:0]=3'b100 to stop the packet generator. Clear counters.
  15. Repeat steps 7 through 11 to simulate packet transfer for each of the instantiated IPs.
  16. Perform Avalon® memory-mapped interface test. Write and read Ethernet IP registers.
    • 0x104: Scratch register
    • 0x108: IP soft reset register
    • 0x214: TX MAX source address register [31:0]
    • 0x218: TX MAX source address register [47:32]
    • 0x21C: RX MAX frame size register
  17. Perform Avalon® memory-mapped interface 2 test to read and write operation transceiver registers.
  18. Repeat steps 13 and 14 for each instantiated IP in a sequential order.
The following sample output illustrates a successful simulation test run. 
---TX reset sequence completed -----
---RX reset sequence completed --------
---Starting Data mode after completing AN -------IP_INST[  0] Test    0;   ---Total     16 packets to send-----
------IP_INST[  0] Start pkt gen TX-----
The time now is 7020000ns 

------Checking Packet TX/RX result-----
------------  16 packets Sent;     0 packets Received--------
------ --- ALL 6  packets Sent out---
------------  16 packets Sent;     2 packets Received--------
------------  16 packets Sent;    16 packets Received--------
------ ---ALL 16 packets Received---
------TX/RX packet check OK---

---IP_INST[1] Test    0;  
 ---Total 16 packets to send-----
------IP_INST[1] Start pkt gen TX-----
------Checking Packet TX/RX result-----
------------  16 packets Sent;     0 packets Received--------
----------ALL 16  packets Sent out---
------------  16 packets Sent;  0 packets Received--------
------------  16 packets Sent;  16 packets Received--------
----------ALL 16  packets Received---
------TX/RX packet check OK---

****Starting AVMM Read/Write****
====>MATCH!  Read addr = 00000104, ReaddataValid = 1 Readdata = abcdef01 Expected_Readdata = abcdef01 

====>MATCH!  Read addr = 000001f0, ReaddataValid = 1 Readdata = 00000000 Expected_Readdata = 00000000 

====>MATCH!  Read addr = 00100004, ReaddataValid = 1 Readdata = c232d284 Expected_Readdata = c232d284 

====>MATCH!  Read addr = 00100008, ReaddataValid = 1 Readdata = 53aefda7 Expected_Readdata = 53aefda7 

====>MATCH!  Read addr = 00100080, ReaddataValid = 1 Readdata = deadc0de Expected_Readdata = deadc0de 

====>MATCH!  Read addr = 00300080, ReaddataValid = 1 Readdata = deadc0de Expected_Readdata = deadc0de 

====>MATCH!  Read addr = 00000af0, ReaddataValid = 1 Readdata = 00000000 Expected_Readdata = 00000000 

====>MATCH!  Read addr = 00005214, ReaddataValid = 1 Readdata = 22334455 Expected_Readdata = 22334455 

====>MATCH!  Read addr = 00005218, ReaddataValid = 1 Readdata = 00000011 Expected_Readdata = 00000011 

====>MATCH!  Read addr = 0000521c, ReaddataValid = 1 Readdata = 000005ee Expected_Readdata = 000005ee 

====>MATCH!  Read addr = 00005214, ReaddataValid = 1 Readdata = 01234567 Expected_Readdata = 01234567 

====>MATCH!  Read addr = 00005218, ReaddataValid = 1 Readdata = 000089ab Expected_Readdata = 000089ab 

7026356ns  Try to access AVMM2 begin...
7026356ns  Try to access AVMM2 begin...
7026356ns  write 0x00000065 to xcvr  0 address 0x008f0010
7026958ns  Try to access AVMM2 end...
7026958ns  read from address 0x008f0010
====>MATCH!  Read addr = 008f0010, ReaddataValid = 1 Readdata = 00000065 Expected_Readdata = 00000065 

7027539ns  Try to access AVMM2 end...
7027540ns  Try to access AVMM2 begin...
7027540ns  write 0x00000066 to xcvr  1 address 0x009f0011
7028141ns  Try to access AVMM2 end...
7028142ns  read from address 0x009f0011
====>MATCH!  Read addr = 009f0011, ReaddataValid = 1 Readdata = 00000066 Expected_Readdata = 00000066 

7028723ns  Try to access AVMM2 end...
7028724ns  Try to access AVMM2 begin...
7028724ns  write 0x00000067 to xcvr  2 address 0x00af0012
7029325ns  Try to access AVMM2 end...
7029326ns  read from address 0x00af0012
====>MATCH!  Read addr = 00af0012, ReaddataValid = 1 Readdata = 00000067 Expected_Readdata = 00000067 

7029907ns  Try to access AVMM2 end...
7029908ns  Try to access AVMM2 begin...
7029908ns  write 0x00000068 to xcvr  3 address 0x00bf0013
The time now is 7030000ns 

7030509ns  Try to access AVMM2 end...
7030510ns  read from address 0x00bf0013
====>MATCH!  Read addr = 00bf0013, ReaddataValid = 1 Readdata = 00000068 Expected_Readdata = 00000068 

7031091ns  Try to access AVMM2 end...
7031092ns  Try to access AVMM2 begin...
7031092ns  write 0x00000069 to xcvr  4 address 0x00cf0014
7031693ns  Try to access AVMM2 end...
7031694ns  read from address 0x00cf0014
====>MATCH!  Read addr = 00cf0014, ReaddataValid = 1 Readdata = 00000069 Expected_Readdata = 00000069 

7032274ns  Try to access AVMM2 end...
7032275ns  Try to access AVMM2 begin...
7032275ns  write 0x0000006a to xcvr  5 address 0x00df0015
7032876ns  Try to access AVMM2 end...
7032877ns  read from address 0x00df0015
====>MATCH!  Read addr = 00df0015, ReaddataValid = 1 Readdata = 0000006a Expected_Readdata = 0000006a 

7033458ns  Try to access AVMM2 end...
7033459ns  Try to access AVMM2 begin...
7033459ns  write 0x0000006b to xcvr  6 address 0x00ef0016
7034060ns  Try to access AVMM2 end...
7034061ns  read from address 0x00ef0016
====>MATCH!  Read addr = 00ef0016, ReaddataValid = 1 Readdata = 0000006b Expected_Readdata = 0000006b 

7034642ns  Try to access AVMM2 end...
7034643ns  Try to access AVMM2 begin...
7034643ns  write 0x0000006c to xcvr  7 address 0x00ff0017
7035244ns  Try to access AVMM2 end...
7035245ns  read from address 0x00ff0017
====>MATCH!  Read addr = 00ff0017, ReaddataValid = 1 Readdata = 0000006c Expected_Readdata = 0000006c 

7035826ns  Try to access AVMM2 end...
**** AVMM Read/Write Operation Completed for IP_INST[  0]****
****Starting AVMM Read/Write****
====>MATCH!  Read addr = 01000104, ReaddataValid = 1 Readdata = abcdef01 Expected_Readdata = abcdef01 

====>MATCH!  Read addr = 010001f0, ReaddataValid = 1 Readdata = 00000000 Expected_Readdata = 00000000 

====>MATCH!  Read addr = 01100004, ReaddataValid = 1 Readdata = b50c786a Expected_Readdata = b50c786a 

====>MATCH!  Read addr = 01100008, ReaddataValid = 1 Readdata = d6bee8ad Expected_Readdata = d6bee8ad 

====>MATCH!  Read addr = 01100080, ReaddataValid = 1 Readdata = deadc0de Expected_Readdata = deadc0de 

====>MATCH!  Read addr = 01300080, ReaddataValid = 1 Readdata = deadc0de Expected_Readdata = deadc0de 

====>MATCH!  Read addr = 01000af0, ReaddataValid = 1 Readdata = 00000000 Expected_Readdata = 00000000 

====>MATCH!  Read addr = 01005214, ReaddataValid = 1 Readdata = 22334455 Expected_Readdata = 22334455 

====>MATCH!  Read addr = 01005218, ReaddataValid = 1 Readdata = 00000011 Expected_Readdata = 00000011 

====>MATCH!  Read addr = 0100521c, ReaddataValid = 1 Readdata = 000005ee Expected_Readdata = 000005ee 

The time now is 7040000ns 

====>MATCH!  Read addr = 01005214, ReaddataValid = 1 Readdata = 01234567 Expected_Readdata = 01234567 

====>MATCH!  Read addr = 01005218, ReaddataValid = 1 Readdata = 000089ab Expected_Readdata = 000089ab 

7040852ns  Try to access AVMM2 begin...
7040852ns  Try to access AVMM2 begin...
7040852ns  write 0x00000065 to xcvr  0 address 0x018f0010
7041454ns  Try to access AVMM2 end...
7041454ns  read from address 0x018f0010
====>MATCH!  Read addr = 018f0010, ReaddataValid = 1 Readdata = 00000065 Expected_Readdata = 00000065 

7042035ns  Try to access AVMM2 end...
7042036ns  Try to access AVMM2 begin...
7042036ns  write 0x00000066 to xcvr  1 address 0x019f0011
7042637ns  Try to access AVMM2 end...
7042638ns  read from address 0x019f0011
====>MATCH!  Read addr = 019f0011, ReaddataValid = 1 Readdata = 00000066 Expected_Readdata = 00000066 

7043219ns  Try to access AVMM2 end...
7043220ns  Try to access AVMM2 begin...
7043220ns  write 0x00000067 to xcvr  2 address 0x01af0012
7043821ns  Try to access AVMM2 end...
7043822ns  read from address 0x01af0012
====>MATCH!  Read addr = 01af0012, ReaddataValid = 1 Readdata = 00000067 Expected_Readdata = 00000067 

7044403ns  Try to access AVMM2 end...
7044404ns  Try to access AVMM2 begin...
7044404ns  write 0x00000068 to xcvr  3 address 0x01bf0013
7045005ns  Try to access AVMM2 end...
7045006ns  read from address 0x01bf0013
====>MATCH!  Read addr = 01bf0013, ReaddataValid = 1 Readdata = 00000068 Expected_Readdata = 00000068 

7045587ns  Try to access AVMM2 end...
7045588ns  Try to access AVMM2 begin...
7045588ns  write 0x00000069 to xcvr  4 address 0x01cf0014
7046189ns  Try to access AVMM2 end...
7046190ns  read from address 0x01cf0014
====>MATCH!  Read addr = 01cf0014, ReaddataValid = 1 Readdata = 00000069 Expected_Readdata = 00000069 

7046770ns  Try to access AVMM2 end...
7046771ns  Try to access AVMM2 begin...
7046771ns  write 0x0000006a to xcvr  5 address 0x01df0015
7047372ns  Try to access AVMM2 end...
7047373ns  read from address 0x01df0015
====>MATCH!  Read addr = 01df0015, ReaddataValid = 1 Readdata = 0000006a Expected_Readdata = 0000006a 

7047954ns  Try to access AVMM2 end...
7047955ns  Try to access AVMM2 begin...
7047955ns  write 0x0000006b to xcvr  6 address 0x01ef0016
7048556ns  Try to access AVMM2 end...
7048557ns  read from address 0x01ef0016
====>MATCH!  Read addr = 01ef0016, ReaddataValid = 1 Readdata = 0000006b Expected_Readdata = 0000006b 

7049138ns  Try to access AVMM2 end...
7049139ns  Try to access AVMM2 begin...
7049139ns  write 0x0000006c to xcvr  7 address 0x01ff0017
7049740ns  Try to access AVMM2 end...
7049741ns  read from address 0x01ff0017
The time now is 7050000ns 

====>MATCH!  Read addr = 01ff0017, ReaddataValid = 1 Readdata = 0000006c Expected_Readdata = 0000006c 

7050322ns  Try to access AVMM2 end...
**** AVMM Read/Write Operation Completed for IP_INST[  1]****
** Testbench complete
**
Note: The simulation completion may take a longer time. To confirm the simulation is progressing successfully, verify the intermediate outputs from the System Console such as bringing the base and AN/LT IP out of resets, IP resetting sequence, Auto-negotiation and link training auto-connection completion, and others.
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