1. Quick Start Guide
|Intel® Quartus® Prime Design Suite 23.1|
|IP Version 9.0.0|
You can generate a design example for any supported variants including design examples with Media Access Controller (MAC) interface, Physical Coding Sublayer (PCS) interface, Optical Transport Network (OTN) interface, and Flexible Ethernet (FlexE) interface for various Ethernet modes and optional FEC mode. In your design example, you can also enable the Precision Time Protocol (PTP) and auto-negotiation and link training options. For a list of supported configurations in the current Intel® Quartus® Prime Pro Edition software version, refer to the Variant Selection table in the F-Tile Ethernet Intel FPGA Hard IP User Guide.
- Design Example: Single IP Core Instantiation
- Design Example: Single IP Core Instantiation with Precision Time Protocol
- Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
- Design Example: Multiple IP Core Instantiation
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