F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

ID 683804
Date 4/03/2023
Document Table of Contents

2. Design Example: Single IP Core Instantiation

The single instance IP core design example supports all F-tile supported Ethernet rates and demonstrates the basic functions of the F-Tile Ethernet Intel FPGA Hard IP.

To generate the design example, you must first set the parameter values for the IP core variation you intend to generate in your end product. Generating the design example creates a copy of the IP core; the testbench and hardware design example use this variation as the DUT. If your parameter values for the DUT don't match the parameter values in your end product, the design example you generate does not exercise the IP core variation you intend.

The following IP parameter settings were used to generate this design example:
Table 5.  IP Parameters for 100G Ethernet Mode with 2 Lanes Design ExampleTable specifies parameter settings used to generate this design example.
Selected IP Parameter Settings Value
General Options
PMA type FGT
Ethernet mode 100GE-2
Client interface MAC segmented
FEC mode

IEEE 802.3 RS(544,514) (CL134)

PMA reference frequency 156.25
System PLL frequency 830.078125

For more information about steps on how to generate a design example, refer to the Generating the Design Example.

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