1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design 7. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 8. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
6. Design Example: Two Separate Instances of Auto-Negotiation and Link Training and Ethernet IP Design
1.3. Simulating the Design Example Testbench
You can compile and simulate the design by running a simulation script from the command prompt.
Figure 9. Procedure
- At the command prompt, change the working directory to <design_example_dir>/example_testbench.
- Run the simulation script for the supported simulator of your choice. The script compiles and runs the testbench in the simulator. Refer to the table Steps to Simulate the Testbench.
- Analyze the results. The successful testbench displays "Simulation Passed".
Table 2. Steps to Simulate the Testbench Simulator Instructions Synopsys* VCS* In the command line, type:
Synopsys* VCS* MX In the command line, type:
Use this script when the design contains Verilog HDL and System Verilog with VHDL.
ModelSim* SE or QuestaSim* or Questa* Intel® FPGA Edition In the command line, type:
vsim -do run_vsim.doIf you prefer to simulate without bringing up the GUI, type:
vsim -c -do run_vsim.do
Xcelium* In the command line, type:
Aldec Riviera-PRO* 1 In the command line, type
vsim -c -do run_rivierasim.do
A successful simulation ends with the following message:
After successful completion, you can analyze the results.
Fast Sim Model for FGT Variants
Fast Sim Model for FHT Variants
1 Only Riviera 2022.10 is supported
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