F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

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ID 683804
Date 6/20/2022
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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example: Single IP Core Instantiation 3. Design Example: Single IP Core Instantiation with Precision Time Protocol 4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training 5. Design Example: Multiple IP Core Instantiation 6. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives 7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide
1. Quick Start Guide x
1.1. Generating the Design 1.2. Directory Structure 1.3. Generating Tile Files 1.4. Simulating the Design Example Testbench 1.5. Hardware and Software Requirements 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example 1.8. Register Maps
1.1. Generating the Design x
1.1.1. Generating Single IP Instance Design 1.1.2. Generating Multiple IP Instance Design
1.4. Simulating the Design Example Testbench x
1.4.1. Fast Sim Model for FGT Variants
2. Design Example: Single IP Core Instantiation x
2.1. Features 2.2. Functional Description 2.3. Simulation 2.4. Packet Client Registers
2.2. Functional Description x
2.2.1. Variation: F-Tile Ethernet Intel FPGA Hard IP with FHT PMA
2.3. Simulation x
2.3.1. Simulation Testbench Flow for MAC Mode 2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes
3. Design Example: Single IP Core Instantiation with Precision Time Protocol x
3.1. Features 3.2. Functional Description 3.3. Simulation 3.4. Hardware Design Example 3.5. Registers
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training x
4.1. Features 4.2. Functional Description 4.3. Simulation 4.4. QSF Assignments 4.5. Hardware Design Example
5. Design Example: Multiple IP Core Instantiation x
5.1. Features 5.2. Functional Description 5.3. Simulation
1. Quick Start Guide
2. Design Example: Single IP Core Instantiation
3. Design Example: Single IP Core Instantiation with Precision Time Protocol
4. Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training
5. Design Example: Multiple IP Core Instantiation
6. F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide Archives
7. Document Revision History for the F-Tile Ethernet Intel FPGA Hard IP Design Example User Guide

1.8. Register Maps

This section displays the available register address range for F-Tile Ethernet Intel FPGA Hard IP and F-Tile Auto-Negotiation and Link Training for Ethernet Intel® FPGA IPs.
The F-Tile Ethernet Intel FPGA Hard IP supports up to 16 Ethernet IP instances. The address range for each IP instance is shown in the Register Map for Multi-Rate IP Instances, PTP, and AN/LT table. The table also displays the address range for PTP-related blocks and auto-negotiation and link training (AN/LT).
Note: The PTP and AN/LT address range is the same regardless of whether the PTP and AN/LT features are enabled or not.
Table 3.  Register Map for Multi-Instance IP Design Examples, PTP, and AN/LT The address range is specified as a byte address.
Address Range [28:0] Module
0x0000_0000 - 0x00FF_FFFC Ethernet IP : Instance 0
0x0100_0000 - 0x01FF_FFFC Ethernet IP : Instance 1
0x0200_0000 - 0x02FF_FFFC Ethernet IP : Instance 2
0x0300_0000 - 0x03FF_FFFC Ethernet IP : Instance 3
0x0400_0000 - 0x04FF_FFFC Ethernet IP : Instance 4
0x0500_0000 - 0x05FF_FFFC Ethernet IP : Instance 5
0x0600_0000 - 0x06FF_FFFC Ethernet IP : Instance 6
0x0700_0000 - 0x07FF_FFFC Ethernet IP : Instance 7
0x0800_0000 - 0x08FF_FFFC Ethernet IP : Instance 8
0x0900_0000 - 0x09FF_FFFC Ethernet IP : Instance 9
0x0A00_0000 - 0x0AFF_FFFC Ethernet IP : Instance 10
0x0B00_0000 - 0x0BFF_FFFC Ethernet IP : Instance 11
0x0C00_0000 - 0x0CFF_FFFC Ethernet IP : Instance 12
0x0D00_0000 - 0x0DFF_FFFC Ethernet IP : Instance 13
0x0E00_0000 - 0x0EFF_FFFC Ethernet IP : Instance 14
0x0F00_0000 - 0x0FFF_FFFC Ethernet IP : Instance 15
0x1000_0000 - 0x1000_FFFC PTP Master TOD registers
0x1001_5000 - 0x1001_5FFC PTP Adapter: Asymmetry Delay
0x1002_5000 - 0x1002_5FFC PTP Adapter: Peer-to-Peer MeanPathDelay
0x1003_0000 - 0x100F_FFFC Reserved
0x1010_0000 - 0x101F_FFFC Auto-negotiation and link training

The table below displays the register address map within a single Ethernet IP instance.

Table 4.  Register Address Map for Single Ethernet IP InstanceThe address range is specified as a byte address.
Address Range [28:0] Module
0x0000_0000 - 0x0000_FFFC Ethernet reconfiguration interface
0x0001_0000 - 0x000F_FFFC Reserved
0x0010_0000 - 0x007F_FFFC Packet Client
0x0080_0000 - 0x008F_FFFC Transceiver reconfiguration interface for lane 0
0x0090_0000 - 0x009F_FFFC Transceiver reconfiguration interface for lane 1
0x00A0_0000 - 0x00AF_FFFC Transceiver reconfiguration interface for lane 2
0x00B0_0000 - 0x00BF_FFFC Transceiver reconfiguration interface for lane 3
0x00C0_0000 - 0x00CF_FFFC Transceiver reconfiguration interface for lane 4
0x00D0_0000 - 0x00DF_FFFC Transceiver reconfiguration interface for lane 5
0x00E0_0000 - 0x00EF_FFFC Transceiver reconfiguration interface for lane 6
0x00F0_0000 - 0x00FF_FFFC Transceiver reconfiguration interface for lane 7

For example, the Packet Client base address in the 2nd Ethernet IP instance is equivalent to 0x0100_0000 + 0x0010_0000 = 0x0110_0000.

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