F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

ID 683804
Date 6/20/2022
Public

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2.4. Packet Client Registers

Table 6.  Packet Client Registers for MAC Segmented Interface and MAC Avalon® ST InterfaceYou can customize the F-Tile Ethernet Intel FPGA Hard IP hardware design example by programming the packet client registers.
Note: All address offsets are specified in the byte address format.
Address Name Bit Offset Default Value Access Description
0x00 hw_pc_ctrl 0 1'b0 RW Indicates start and stop of the TX packet.
  • 0: Stop packet generator
  • 1: Start packet generator
2 1'b0 RW Indicates packet transmission mode.
  • 0: One time mode
  • 1: Continuous mode

When you switch from continuous to one time mode, you must set hw_pc_ctrl[0] to 1 to ensure the pending packet transmission is completed.

4 1'b0 RW Indicates packet client loopback.
  • 0: Packet generator data path
  • 1: Loopback client data path
6 1'b0 RW Indicates the snapshot status for all statistics counter registers.
  • 0: No snapshot
  • 1: Snapshot available
7 1'b0 RW Indicates the clear status of the snapshot registers.
  • 0: Do not clear the internal registers
  • 1: Clear the internal registers
8 1'b0 RW Indicates the EOP of TX packet and clears counters.
0x04 hw_test_loop_cnt [15:0] 16'd1 RW Indicates the number of times the ROM packet data are sent.
0x08 hw_test_rom_addr [15:0] 16'd0 RW ROM packet data start address
[31:16] 16'd0 RW ROM packet data end address
0x20 stat_tx_sop_cnt_lsb [31:0] 32'b0 RO Lower 32-bits of the TX start-of-packet (SOP) counter
0x24 stat_tx_sop_cnt_msb [31:0] 32'b0 RO Upper 32-bits of the TX start-of-packet (SOP) counter
0x28 stat_tx_eop_cnt_lsb [31:0] 32'b0 RO Lower 32-bits of the TX end-of-packet (EOP) counter
0x2C stat_tx_eop_cnt_msb [31:0] 32'b0 RO Upper 32-bits of the TX end-of-packet (EOP) counter
0x30 stat_tx_err_cnt_lsb [31:0] 32'b0 RO Lower 32-bits of the TX error counter
0x34 stat_tx_err_cnt_msb [31:0] 32'b0 RO Upper 32-bits of the TX error counter
0x38 stat_rx_sop_cnt_lsb [31:0] 32'b0 RO Lower 32-bits of the RX start-of-packet (SOP) counter
0x3C stat_rx_sop_cnt_msb [31:0] 32'b0 RO Upper 32-bits of the RX start-of-packet (SOP) counter
0x40 stat_rx_eop_cnt_lsb [31:0] 32'b0 RO Lower 32-bits of the RX end-of-packet (EOP) counter
0x44 stat_rx_eop_cnt_msb [31:0] 32'b0 RO Upper 32-bits of the RX end-of-packet (EOP) counter
0x48 stat_rx_err_cnt_lsb [31:0] 32'b0 RO Lower 32-bits of the RX error counter
0x4C stat_rx_err_cnt_lsb [31:0] 32'b0 RO Upper 32-bits of the RX error counter
Table 7.  Packet Client Registers for PCS, OTN, and FlexE InterfaceYou can customize the F-Tile Ethernet Intel FPGA Hard IP hardware design example by programming the packet client registers.
Note: All address offsets are specified in the byte address format.
Address Name Bit Offset Default Value Access Description
0x10 cfg_start_pkt_gen 0 1'b0 RW Indicates start and stop of the TX packet.
  • 0: Stop packet generator.
  • 1: Start packet generator.
0x58 cfg_clear_counters 0 1'b0 RW When set, clears packet generator counters.
0x18 stat_tx_sop_cnt [31:0] 32'b0 RO Lower 32-bits of the TX start-of-packet (SOP) counter
0x1C stat_tx_sop_cnt [63:32] 32'b0 RO Upper 32-bits of the TX start-of packet (SOP) counter
0x20 stat_tx_eop_cnt [31:0] 32'b0 RO Lower 32-bits of the TX end-of-packet (EOP) counter
0x24 stat_tx_eop_cnt [63:32] 32'b0 RO Upper 32-bits of the TX end-of-packet (EOP) counter
0x30 stat_rx_sop_cnt [31:0] 32'b0 RO Lower 32-bits of the RX start-of-packet (SOP) counter
0x34 stat_rx_sop_cnt [63:32] 32'b0 RO Upper 32-bits of the RX start-of-packet (SOP) counter
0x38 stat_rx_eop_cnt [31:0] 32'b0 RO Lower 32-bits of the RX end-of-packet (EOP) counter
0x3C stat_rx_eop_cnt [63:32] 32'b0 RO Upper 32-bits of the RX end-of-packet (EOP) counter
0x50 stat_rx_err_cnt [31:0] 32'b0 RO Lower 32-bits of the RX error status
0x54 stat_rx_err_cnt [63:32] 32'b0 RO Upper 32-bits of the RX error status

For information about register base and offset addresses, refer to the F-Tile Ethernet Intel FPGA Hard IP User Guide.

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