F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

ID 683804
Date 6/20/2022

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3. Design Example: Single IP Core Instantiation with Precision Time Protocol

The single instance IP core design example supports Ethernet rates with enabled Precision Time Protocol (PTP) and demonstrates the basic functions of the F-Tile Ethernet Intel FPGA Hard IP.

To generate the design example, you must first set the parameter values for the IP core variation you intend to generate in your end product. Generating the design example creates a copy of the IP core; the testbench and hardware design example use this variation as the DUT. If your parameter values for the DUT don't match the parameter values in your end product, the design example you generate does not exercise the IP core variation you intend.

The following IP parameter settings were used to generate this design example:
Table 8.  Selected IP Parameter SettingsTable specifies parameter settings used to generate this design example.
Selected IP Parameter Settings Value
General Options
PMA type FGT
Ethernet mode 400GE-8
Client interface MAC segmented
FEC mode Ethernet Technology Consortium RS(272,514)
PMA reference frequency 156.25
System PLL frequency 830.078125
MAC Options
Enable IEEE 1588 PTP

Timestamp accuracy mode Advanced
Timestamp fingerprint width 8

For more information about steps of how to generate a design example, refer to the Generating the Design Example.