||Made the following changes:
- Added support for the Xcelium* simulator.
- Updated quick start guide sub-sections:
- Globally added support for the Agilex I-Series Transceiver-SoC Development Kit.
- Updated Generating Tile Files.
- Added new topic: Compiling and Configuring the Design Example in Hardware.
- Updated steps in Testing the F-Tile Ethernet Intel FPGA Hard IP Hardware Design Example.
- Updated Design Example: Single IP Core Instantiation with Precision Time Protocol:
- Added note about i_reconfig_clk clock frequency limitation.
- Revised the sample output in the Simulation section.
- Added new topic: Hardware Design Example.
- Updated Design Example: Single IP Core Instantiation with Auto-Negotiation and Link Training:
- Replaced the placement assignments with the colocate assignments.
- Updated simulation flow.
- Updated QSF assignments.
- Added pin assignment requirement for AN/LT designs in Generating Tile Files.
- Updated the list of supported simulators in Simulating the Design Example Testbench.
- Added new topics:
- Fast Sim Model
- Testing the Hardware Design Example
- Register Maps
- Simulation Testbench Flow for PCS, OTN, and FlexE Modes
- Updated register descriptions in Packet Client Registers.
- Updated PTP-related Registers section. Address offset is specified as a byte address.
- Added new design examples: Single IP Core Instantiation with Auto-Negotiation and Link Training