F-Tile Ethernet Intel® FPGA Hard IP Design Example User Guide

ID 683804
Date 6/20/2022
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

2.3.2. Simulation Testbench Flow for PCS, OTN, and FlexE Modes

The following steps show the simulation testbench flow for PCS, OTN, and FlexE modes:
  1. Assert global reset (i_rst_n) to reset the F-Tile Ethernet Intel FPGA Hard IP.
  2. Wait until resets acknowledgment. The o_rst_ack_n signal goes low.
  3. Deasserts the global reset.
  4. Wait until o_tx_lanes_stable bit is set to 1, indicating TX path is ready.
  5. Wait until o_rx_pcs_ready bit is set to 1, indicating RX path is ready.
    Note: In non-MAC mode, the packet client sends out idle data in MII/PCS66 format.
  6. Read TX packet data information from 0x00 - 0x34 registers in sequential order.
    • 0x00: Set hw_pc_ctrl[6] = 1'b1 to enable snapshot bit to read the TX packet statistics.
    • 0x020/0x24: TX start of packet counter (LSB/MSB)
    • 0x28/0x2C: TX end of packet counter (LSB/MSB)
    • 0x00: Set hw_pc_ctrl[6] = 1'b0 to disable snapshot bit.
  7. Read RX packet data information from 0x38 - 0x4C registers in sequential order.
    • 0x00: Set hw_pc_ctrl[6] = 1'b1 to enable snapshot bit to read the RX packet statistics.
    • 0x38/0x3C: RX start of packet counter (LSB/MSB)
    • 0x40/0x44: RX end of packet counter (LSB/MSB)
    • 0x48/0x4C: RX error counter (LSB/MSB)
    • 0x00: Set hw_pc_ctrl[6] = 1'b0 to disable snapshot bit.
  8. Compare the counters to ensure 16 packets were sent and received.
  9. Instruct packet client to stop data transmission. Write cfg_start_pkt_gen[0]=1'b1 to stop the packet generator. Clear counters.
  10. Perform Avalon® memory-mapped interface test. Write and read Ethernet IP registers.
    • 0x104: Scratch register
    • 0x108: Ethernet IP soft reset register
    • 0x004: Ethernet IP debug configuration control register
    • 0x008: Ethernet IP enable/clock gating configuration register
  11. Perform Avalon® memory-mapped interface 2 test. Write and read transceiver registers.