Interlaken (2nd Generation) Intel® Agilex™ FPGA IP Design Example User Guide

ID 683800
Date 8/03/2022
Public

2.2. Interface Signals

Table 5.  Design Example Interface Signals
Port Name Direction Width (Bits) Description
mgmt_clk Input 1 System clock input. Clock frequency must be 100 MHz.
pll_ref_clk / pll_ref_clk[1:0] 2 Input 1/2 Transceiver reference clock. Drives the RX CDR PLL.
Note: pll_ref_clk[1] is only available when you enable Preserve unused transceiver channels for PAM4 parameter in E-tile PAM4 mode IP variations.
rx_pin Input Number of lanes Receiver SERDES data pin.
tx_pin Output Number of lanes Transmit SERDES data pin.
rx_pin_n Input Number of lanes Receiver SERDES data pin.

This signal is only available in E-tile PAM4 mode device variations.

tx_pin_n Output Number of lanes Transmit SERDES data pin.

This signal is only available in E-tile PAM4 mode device variations.

mac_clk_pll_ref Input 1 This signal must be driven by a PLL and must use the same clock source that drives the pll_ref_clk.

This signal is only available in E-tile PAM4 mode device variations.

usr_pb_reset_n Input 1 System reset.
2 When you enable Preserve unused transceiver channels for PAM4 parameter, an additional reference clock port is added to preserve the unused PAM4 slave channel.

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