Interlaken (2nd Generation) Intel® Agilex™ FPGA IP Design Example User Guide

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ID 683800
Date 8/03/2022
Public

2.1. Design Example Behavior

To test the design in hardware, type the following commands in the System Console::
  1. Source the setup file:
    % source  <design_example>uflex_ilk_0_example_design/example_design/hwtest/sysconsole_testbench.tcl
  2. Run the test:
    
    % run_example_design
  3. The Interlaken (2nd Generation) hardware design example completes the following steps:
    1. Resets the Interlaken (2nd Generation) IP.
    2. Configures the Interlaken (2nd Generation) IP in internal loopback mode.
    3. Sends a stream of Interlaken packets with predefined data in the payload to the TX user data transfer interface of the IP core.
    4. Checks the received packets and reports the status. The packet checker included in the hardware design example provides the following basic packet checking capabilities:
    • Checks that the transmitted packet sequence is correct.
    • Checks that the received data matches the expected values by ensuring both the start of packet (SOP) and end of packet (EOP) counts align while data is being transmitted and received.

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