1.3. Hardware Design Example Components
The example design connects system and PLL reference clocks and required design components. The example design configures the IP core in internal loopback mode and generates packets on the IP core TX user data transfer interface. The IP core sends these packets on the internal loopback path through the transceiver.
After the IP core receiver receives the packets on the loopback path, it processes the Interlaken packets and transmits them on the RX user data transfer interface. The example design checks that the packets received and transmitted match.
The hardware example design includes external PLLs. You can examine the clear text files to view sample code that implements one possible method to connect external PLLs to the Interlaken (2nd Generation) FPGA IP.
- Interlaken (2nd Generation) FPGA IP
- Packet Generator and Packet Checker
- JTAG controller that communicates with System Console. You communicate with the client logic through the System Console.
The Interlaken (2nd Generation) hardware design example that targets an E-tile PAM4 mode variations requires an additional clock mac_clkin that the IO PLL generates. This PLL must use the same reference clock that drives the pll_ref_clk.
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