Interlaken (2nd Generation) Intel® Agilex™ FPGA IP Design Example User Guide

ID 683800
Date 8/03/2022
Public

1.3. Hardware Design Example Components

The example design connects system and PLL reference clocks and required design components. The example design configures the IP core in internal loopback mode and generates packets on the IP core TX user data transfer interface. The IP core sends these packets on the internal loopback path through the transceiver.

After the IP core receiver receives the packets on the loopback path, it processes the Interlaken packets and transmits them on the RX user data transfer interface. The example design checks that the packets received and transmitted match.

The hardware example design includes external PLLs. You can examine the clear text files to view sample code that implements one possible method to connect external PLLs to the Interlaken (2nd Generation) FPGA IP.

The Interlaken (2nd Generation) hardware design example includes the following components:
  1. Interlaken (2nd Generation) FPGA IP
  2. Packet Generator and Packet Checker
  3. JTAG controller that communicates with System Console. You communicate with the client logic through the System Console.
Figure 4.  Interlaken (2nd Generation) Hardware Design Example High Level Block Diagram for E-tile NRZ Mode Variations

The Interlaken (2nd Generation) hardware design example that targets an E-tile PAM4 mode variations requires an additional clock mac_clkin that the IO PLL generates. This PLL must use the same reference clock that drives the pll_ref_clk.

Figure 5.  Interlaken (2nd Generation) Hardware Design Example High Level Block Diagram for E-tile PAM4 Mode Variations
For E-tile PAM4 mode variations, when you enable the Preserve unused transceiver channels for PAM4 parameter, an additional reference clock port is added (pll_ref_clk [1]). This port must be driven at the same frequency as defined in the IP parameter editor (Reference clock frequency for preserved channels). The Preserve unused transceiver channels for PAM4 is optional. The pin and related constraints assigned to this clock is visible in the QSF when you select Intel® Stratix® 10 or Intel® Agilex™ development kit for design generation.
Note: For design example simulation, the testbench always defines same frequency for pll_ref_clk[0] and pll_ref_clk[1].

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