Interlaken (2nd Generation) Intel® Agilex™ FPGA IP Design Example User Guide

ID 683800
Date 8/03/2022
Public

1.7. Testing the Hardware Design Example

After you compile the Interlaken (2nd Generation) Intel® FPGA IP core design example and configure your device, you can use the System Console to program the IP core and its embedded Native PHY IP core registers.

Follow these steps to bring up the System Console and test the hardware design example:

  1. In the Intel® Quartus® Prime Pro Edition software, on the Tools menu, click System Debugging Tools > System Console.
  2. Change to the <design_example_installation_dir>example_design/hwtest directory.
  3. To open a connection to the JTAG master, type the following command:
    source sysconsole_testbench.tcl
  4. You can turn on internal serial loopback mode with the following design example commands:
    1. stat: Prints general status info.
    2. sys_reset: Resets the system.
    3. loop_on: Turns on internal serial loopback.
    4. run_example_design: Runs the design example.
    Note: You must run loop_on command before run_example_design command. The run_example_design runs the following commands in a sequence: sys_reset->stat->gen_on->stat->gen_off.
    Note: When you select the Enable adaptation load soft IP option, the run_example_design command performs the initial adaptation calibration on RX side by running the run_load_PMA_configuration command.
  5. You can turn off internal serial loopback mode with the following design example command:
    1. loop_off: Turns off internal serial loopback.
  6. You can program the IP core with the following additional design example commands:
    1. gen_on: Enables packet generator.
    2. gen_off: Disables packet generator.
    3. run_test_loop: Runs the test for <N> times for E-tile NRZ and PAM4 variations.
    4. clear_err: Clears all sticky error bits.
    5. set_test_mode <min_okt_size> <max_pkt_size> <step> <num_to_run>: Sets up test to run in a specific mode.
    6. get_test_mode: Prints the current test mode.
    7. set_burst_size <burst_size>: Sets burst size in bytes.
    8. get_burst_size: Prints burst size information.
    The successful test prints HW_TEST:PASS message. Below is the passing criteria for a test run:
    • No errors for CRC32, CRC24, and checker.
    • Transmitted SOPs and EOPs should be match with received.
    The following sample output illustrates a successful test run in Interlaken mode:
    __________________________________________________________
    	 INFO: INFO: Stop generating packtes
    __________________________________________________________
    
    
        ==== STATUS REPORT ====
        TX KHz         : 402813
        RX KHz         : 402813
        Freq locks     : 0x0000ff
        TX PLL lock    : 0x000001
        Align          : 0x00c10f
        Rx LOA         : 0x000000
        Tx LOA         : 0x000000
    
        word lock      : 0x0000ff
        sync lock      : 0x0000ff
    
        CRC32 errors   : 0
        CRC24 errors   : 0
        Checker errors : 0
    
        FIFO err flags : 0x000000
        SOPs transmitted   : 1087913770
        EOPs transmitted   : 1087913770
        SOPs received      : 1087913770
        EOPs received      : 1087913770
        ECC corrected      : 0
        ECC error          : 0
    
        Elapsed 161 sec since powerup
    
    HW_TEST : PASS
    The successful test prints HW_TEST : PASS message. Below is the passing criteria for a test run:
    • No errors for CRC32, CRC24, and checker.
    • Transmitted SOPs and EOPs should be match with received.
    The following sample output illustrates a successful test run in Interlaken Look-aside mode:
    __________________________________________________________
    	 INFO: INFO: Stop generating packtes
    __________________________________________________________
    
    
        ==== STATUS REPORT ====
        TX KHz         : 402813
        RX KHz         : 402812
        Freq locks     : 0x000fff
        TX PLL lock    : 0x000001
        Align          : 0x00c10f
        Rx LOA         : 0x000000
        Tx LOA         : 0x000000
    
        word lock      : 0x000fff
        sync lock      : 0x000fff
    
        CRC32 errors   : 0
        CRC24 errors   : 0
        Checker errors : 0
    
        SOPs transmitted   : 461
        EOPs transmitted   : 461
        SOPs received      : 461
        EOPs received      : 461
    
        Elapsed 171 sec since powerup
    
    HW_TEST : PASS	 

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