Interlaken (2nd Generation) Intel® Agilex™ FPGA IP Design Example User Guide

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ID 683800
Date 8/03/2022
Public

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Document Table of Contents
Document Table of Contents x
1. Quick Start Guide 2. Design Example Description 3. Interlaken (2nd Generation) Intel® Agilex™ FPGA IP Design Example User Guide Archives 4. Document Revision History for Interlaken (2nd Generation) Intel® Agilex™ FPGA IP Design Example User Guide
1. Quick Start Guide x
1.1. Hardware and Software Requirements 1.2. Directory Structure 1.3. Hardware Design Example Components 1.4. Generating the Design 1.5. Simulating the Design Example Testbench 1.6. Compiling and Configuring the Design Example in Hardware 1.7. Testing the Hardware Design Example
2. Design Example Description x
2.1. Design Example Behavior 2.2. Interface Signals 2.3. Register Map
1. Quick Start Guide
2. Design Example Description
3. Interlaken (2nd Generation) Intel® Agilex™ FPGA IP Design Example User Guide Archives
4. Document Revision History for Interlaken (2nd Generation) Intel® Agilex™ FPGA IP Design Example User Guide

3. Interlaken (2nd Generation) Intel® Agilex™ FPGA IP Design Example User Guide Archives

IP versions are the same as the Intel® Quartus® Prime Design Suite software versions up to v19.1. From Intel® Quartus® Prime Design Suite software version 19.2 or later, IP cores have a new IP versioning scheme.

If an IP core version is not listed, the user guide for the previous IP core version applies.
Quartus Version IP Core Version User Guide
20.4 20.0.1 Interlaken (2nd Generation) Intel Agilex FPGA IP Design Example User Guide
20.4 20.0.0 Interlaken (2nd Generation) Intel Agilex FPGA IP Design Example User Guide
20.2 19.3.0 Interlaken (2nd Generation) Intel Agilex FPGA IP Design Example User Guide
19.3 19.2.1 Interlaken (2nd Generation) Intel Agilex FPGA IP Design Example User Guide
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