HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/10/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

9.3.1.13. USER_BUFFER_LEVEL (0x12)

Table 134.  USER_BUFFER_LEVEL (0x12)
Name Bit Access Description Reset
Buffer level 31:0 RO Indicates the number of data packets present in the buffer. 0x0