5.2. Source Interfaces

HDMI Intel® FPGA IP User Guide

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Date 4/10/2023

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5.2. Source Interfaces

The table lists the port interfaces of the source.

Table 37. HDMI Source Interfaces `N` is the number of pixels per clock.
Interface	Port Type	Clock Domain	Port	Direction	Description
Reset	Reset	–	`reset`	Input	Main asynchronous reset input.
	Reset	–	`reset_vid`	Input	Reset input for the video domain. Note: This signal is only available when Support FRL = 0.
	Reset	–	`axi4s_reset`	Input	Reset to AXI4-stream to clocked video converter. Note: This signal is only applicable when Enable Active Video Protocol = AXIS-VVP Full
Clock	Clock	–	`ls_clk`	Input	Link speed clock input. The `out_c(3)`, `out_r(2)`, `out_g(1)`, and `out_b(0)`TMDS encoded data outputs run at this clock frequency. `ls_clk` frequency = data rate per lane/ 20 This signal connects to the transceiver output clock only if TMDS bit rate is above the minimum transceiver data rate, which means no oversampling is required. This signal should connect to a PLL output clock that supplies the `ls_clk` frequency if the TMDS bit rate is below the minimum transceiver data rate, which means oversampling is required. In TMDS mode, data rate per lane is a function of pixel frequency and color depth ratio. Data rate per lane = Pixel frequency x 10 x Color depth ratio. 8 bpc: Color depth ratio = 1 10 bpc: Color depth ratio = 1.25 12 bpc: Color depth ratio = 1.5 16 bpc: Color depth ratio = 2 Note: This port is not available when the SUPPORT_FRL parameter is enabled.
	Clock	–	`vid_clk`	Input	Video data clock input. When Support FRL = 0, `vid_clk` frequency = data rate per lane/transceiver width/color depth ratio. For RGB and YCbCr 4:4:4/4:2:2 transport: `vid_clk` frequency = (data rate per lane/transceiver width)/color depth ratio. For YCbCr 4:2:0 transport: `vid_clk` frequency = ((data rate per lane/transceiver width)/color depth ratio)/2. `vid_clk` needs to be synchronous to `ls_clk`. When Support FRL = 1,`vid_clk` frequency can be a fixed clock frequency. Intel recommends to use 225 MHz for the `vid_clk`. `vid_clk` runs at the maximum frequency across all resolutions and FRL rates. The video data is qualified by the `vid_valid` signal. `vid_clk` can be asynchronous to `ls_clk` and `frl_clk`. Refer to Table 41 for more details.
	Clock	–	`tx_clk`	Input	Transceiver recovered clock. Connect this signal to the output clock of the TX transceiver output clock.
	Clock	–	`frl_clk`	Input	Clock supplied to the FRL path. FRL clock frequency = (data rate * number of lane)s / (FRL characters per clock * 18). `frl_clk` needs to be synchronous to `tx_clk`. Note: The number of lanes is always 4. For FRL rates 3, 4, 5, and 6, all 4 FRL lanes are used to transmit data. For FRL rates 1 and 2, only 3 FRL lanes are used to transmit data, and the 4th lane is unused. In Intel® Arria® 10 devices, FRL characters per clock is 16. In Intel® Stratix® 10 devices, FRL characters per clock is 8.
	Clock	–	`audio_clk`	Input	Audio clock input. Connect this signal to `ls_clk` when Support FRL = 0 or to `vid_clk` when Support FRL = 1 by qualifying the slower frequency of `audio_data` with `audio_de`. If you connect this signal to a clock at actual audio sample frequency, you must tie `audio_de` to 1. For audio channels greater than 8, do not drive `audio_clk` at actual audio sample clock; instead drive `audio_clk` with `ls_clk` when Support FRL = 0 or to `vid_clk` when Support FRL = 1, and qualify `audio_data` with `audio_de`. Note: Applicable only when you turn on the Support auxiliary and Support audio parameters.
	Clock	–	`mgmt_clk`	Input	Free-running system clock input (100 MHz). This clock connects to the I²C master and HPD debouncing logic. Note: This signal is not available if you turn off the Include I2C parameter.
	Clock	–	`axi4s_clk`	Input	Clock for AXI4-stream interface. The clock frequency shall be equal or greater than vid_clk frequency. Note: This signal is only applicable when Enable Active Video Protocol = AXIS-VVP Full
Video Data Port	Conduit	`vid_clk`	`vid_data[N*48-1:0]`	Input	Video 48-bit pixel data input port. For N pixels per clock, this port accepts N 48-bit pixels per clock.
	Conduit	`vid_clk`	`vid_de[N-1:0]`	Input	Video data enable input that indicates active picture region.
	Conduit	`vid_clk`	`vid_hsync[N-1:0]`	Input	Video horizontal sync input.
	Conduit	`vid_clk`	`vid_vsync[N-1:0]`	Input	Video vertical sync input.
	Conduit	`vid_clk`	`vid_ready`	Output	Indicates if the TX core is ready to process new data. When `vid_ready` is asserted, the TX core is ready to process new data. Note: This signal is only available when Support FRL = 1. `vid_ready` is always high for 8 bits per component (BPC). This signal toggles for different color depths. For 10 bpc, `vid_ready` is high for 4 out of 5 clock cycles. For 12 bpc, `vid_ready` is high for 2 out of 3 clock cycles. For 16 bpc, `vid_ready` is high for 1 out of 2 clock cycles. Refer to Source Deep Color Implementation When Support FRL = 1 for more details.
	Conduit	`vid_clk`	`vid_valid`	Input	Indicates if the video data is valid. When `vid_clk` is running at the actual pixel clock, this signal should always be asserted. Note: This signal is only available when Support FRL = 1. When you generate the video data at a frequency higher than the actual pixel clock, use `vid_valid` to qualify the validity of the video data. `vid_valid` and `vid_clk` guarantee the exact pixel clock rate. Refer to Valid Video Data for more details.
	Conduit	`vid_clk`	`vid_overflow`	Output	Indicates if the FIFO clocking the data from the video path to the FRL path is overflowing. Under normal operation, this signal is not expected to assert. Reset HDMI TX core if this signal is asserted. Applicable only for FRL mode.
TMDS/FRL Data Port	Conduit	`Support FRL=1: tx_clk` `Support FRL =0: ls_clk`	`out_b[transceiver width-1:0]`	Output	When in TMDS mode, this signal is TMDS encoded blue channel (0) output. When in FRL mode, this signal is FRL lane 0. When Support FRL = 0, transceiver width is configured to 20 bits. When Support FRL = 1, transceiver width is configured to 40 bits. Note: For TMDS mode, only the 20 bits from the least significant bits are used. For FRL mode, all 40 bits are used.
	Conduit	`Support FRL=1: tx_clk` `Support FRL =0: ls_clk`	`out_g[transceiver width-1:0]`	Output	When in TMDS mode, this signal is TMDS encoded green channel (1) output. When in FRL mode, this signal is FRL lane 1. When Support FRL = 0, transceiver width is configured to 20 bits. When Support FRL = 1, transceiver width is configured to 40 bits. Note: For TMDS mode, only the 20 bits from the least significant bits are used. For FRL mode, all 40 bits are used.
	Conduit	`Support FRL=1: tx_clk` `Support FRL =0: ls_clk`	`out_r[transceiver width-1:0]`	Output	When in TMDS mode, this signal is TMDS encoded red channel (2) output. When in FRL mode, this signal is FRL lane 2. When Support FRL = 0, transceiver width is configured to 20 bits. When Support FRL = 1, transceiver width is configured to 40 bits. Note: For TMDS mode, only the 20 bits from the least significant bits are used. For FRL mode, all 40 bits are used.
	Conduit	`Support FRL=1: tx_clk` `Support FRL =0: ls_clk`	`out_c[transceiver width-1:0]`	Output	When in TMDS mode, this signal is TMDS encoded clock channel (3) output. When in FRL mode, this signal is FRL lane 3. When Support FRL = 0, transceiver width is configured to 20 bits. When Support FRL = 1, transceiver width is configured to 40 bits. Note: For TMDS mode, only the 20 bits from the least significant bits are used. For FRL mode, all 40 bits are used.
	Conduit	`-`	`in_lock`	Input	When asserted, the HDMI TX core begins to operate. Synchronize this signal to the same clock domain as reset port. When Support FRL =0, in_lock, reset and reset_vid should run at same clock domain.
Encoder Control Port	Conduit	`Support FRL=1: tx_clk` `Support FRL =0: ls_clk`	`mode`	Input	Encoding mode input. 0: DVI 1: HDMI
	Conduit	`Support FRL=1: tx_clk` `Support FRL =0: ls_clk`	`tmds_bit_clock_ratio`	Input	Indicates if TMDS Bit Rate is greater than 3.4 Gbps in TMDS mode. 0: (TMDS Bit Rate) / (TMDS Clock Rate) ratio is 10 1 = (TMDS Bit Rate) / (TMDS Clock Rate) ratio is 40
	Conduit	`Support FRL=1: tx_clk` `Support FRL =0: ls_clk`	`scrambler_enable`	Input	Enables scrambling. 0: Instructs the source device not to perform scrambling 1: Instructs the source device to perform scrambling
	Conduit	`Support FRL=1: tx_clk` `Support FRL =0: ls_clk`	`ctrl[N*6-1:0]`	Input	DVI control side-band inputs to override the necessary control and synchronization data in the green and red channels.
					Bit-Field	n=0,1.....N-1
					n*6+5	CTL3
					n*6+4	CTL2
					n*6+3	CTL1
					n*6+2	CTL0
					n*6+1	Reserved (0)
					n*6	Reserved (0)

Link Training Control Port	Conduit	`frl_clk`	`scdc_frl_start`	Input	When set to 1, the TX core transmits normal video data. When set to 0, the TX core transmits link training pattern data.
	Conduit	`frl_clk`	`scdc_frl_rate[3:0]`	Input	Specifies the FRL rate (link rate and number of lanes) that the TX core is running. 0: Disable FRL 1: Fixed rate link at 3 Gbps per lane on 3 lanes 2: Fixed rate link at 6 Gbps per lane on 3 lanes 3: Fixed rate link at 6 Gbps per lane on 4 lanes 4: Fixed rate link at 8 Gbps per lane on 4 lanes 5: Fixed rate link at 10 Gbps per lane on 4 lanes 6: Fixed rate link at 12 Gbps per lane on 4 lanes
	Conduit	`frl_clk`	`scdc_frl_pattern[15:0]`	Input	Indicates the link training pattern that each lane on the TX core is transmitting . `scdc_frl_pattern[3:0]`: Link training pattern for lane 0 `scdc_frl_pattern[7:4]`: Link training pattern for lane 1 `scdc_frl_pattern[11:8]`: Link training pattern for lane 2 `scdc_frl_pattern[15:12]`: Link training pattern for lane 3 4’d0: No link training pattern 4’d1: All 1’s pattern 4’d2: All 0’s pattern 4’d3: Nyquist clock pattern 4’d4: TxFFE Compliance Test Pattern 4’d5: LFSR 0 4’d6: LFSR 1 4’d7: LFSR 2 4’d8: LFSR 3
Auxiliary Data Port (Applicable only when you enable Support auxiliary parameter) ⁵	Conduit	`aux_clk`	`aux_ready`	Output	Auxiliary data channel ready output. Asserted high to indicate that the core is ready to accept data.
	Conduit	`aux_clk`	`aux_valid`	Input	Auxiliary data channel valid input to qualify the data.
	Conduit	`aux_clk`	`aux_data[71:0]`	Input	Auxiliary data channel data input. For information about the bit-fields, refer to Figure 22.
	Conduit	`aux_clk`	`aux_sop`	Input	Auxiliary data channel start-of-packet input to mark the beginning of a packet.
	Conduit	`aux_clk`	`aux_eop`	Input	Auxiliary data channel end-of-packet input to mark the end of a packet.
Auxiliary Control Port (Applicable only when you enable Support auxiliary parameter) ⁵	Conduit	`aux_clk`	`gcp[5:0]`	Input	General Control Packet user input. For information about the bit-fields, refer to Table 23.
	Conduit	`aux_clk`	`info_avi[122:0]` (Support FRL = 1) `info_avi[112:0]` (Support FRL = 0)	Input	Auxiliary Video Information InfoFrame user input. For information about the bit-fields, refer to Table 24.
	Conduit	`aux_clk`	`info_vsi[61:0]`	Input	Vendor Specific Information InfoFrame user input. For information about the bit-fields, refer to Table 26.
Audio Port (Applicable only when you enable Support auxiliary and Support audio parameters) ⁵	Conduit	`audio_clk`	`audio_CTS[19:0]`	Input	Audio CTS value input.
	Conduit	`audio_clk`	`audio_N[19:0]`	Input	Audio N value input.
	Conduit	`audio_clk`	`audio_data[255:0]`	Input	Audio data input. For audio channel values, refer to Table 40.
	Conduit	`audio_clk`	`audio_de`	Input	Audio data valid input.
	Conduit	`audio_clk`	`audio_mute`	Input	Audio mute input. No audio will be transmitted when this signal is asserted high.
	Conduit	`aux_clk`	`audio_info_ai[48:0]`	Input	Audio InfoFrame user input. Note: If you provide `audio_info_ai` `[48:0]` using `audio_clk` with actual audio sample frequency, you must synchronize the clock domain to `ls_clk` externally. For information about the bit-fields, refer to Table 28.
	Conduit	`aux_clk`	`audio_metadata[165:0]`	Input	Carries additional information related to 3D audio and MST audio. Note: If you provide `audio_metadata` `[165:0]` using `audio_clk` with actual audio sample frequency, you must synchronize the clock domain to `ls_clk` externally. For information about the bit-fields, refer to Table 29, Table 30, and Table 31.
	Conduit	`audio_clk`	`audio_format[4:0]`	Input	Controls the transmission of the 3D audio and indicates the audio format to be transmitted.
					Bit-Field	Description
					4	Assert to indicate the first 8 channels of each 3D audio sample.
					3:0	For information about the bit-fields, refer to Table 27.
PHY Interface Control Port	Conduit	`Support FRL=1: tx_clk` `Support FRL =0: ls_clk`	`os[1:0]`	Input	Oversampling control signal to control the oversampling factor. Support FRL = 1 0: No oversample. Send this when you are transmitting FRL. 1: 2x oversampling: Send this when you are transmitting TMDS rate between 1 Gb/s < rate ≤ 6 Gb/s 2: 8x oversampling: Send this when you are transmitting TMDS rate ≤ 1 Gb/s Support FRL = 0 0: No oversample. Send this when you are transmitting TMDS rate ≥ 1 Gb/s. 1: 3x oversampling: Send this when you are transmitting data rate between 350 Mb/s ≤ rate < 500 Gb/s 2: 4x oversampling: Send this when you are transmitting data rate between 300 Mb/s ≤ rate < 350 Gb/s 3: 5x oversampling: Send this when you are transmitting data rate between 250 Mb/s ≤ rate < 300 Gb/s or data rate between 500 Mb/s ≤ rate < 1 Gb/s
Hot Plug Detect	Conduit	–	`tx_hpd`	Input	Detects the Hot Plug Detect (HPD) status. This signal should be driven with the same signal to the HPD pin on the HDMI connector.
Hot Plug Detect	Conduit	mgmt_clk	`tx_hpd_req`	Output	The core asserts the `tx_hpd_req` signal if the `tx_hpd` signal holds for more than 100 milliseconds, indicating a valid HPD. The `tx_hpd_req` signal deasserts if the `tx_hpd` signal is not detected.
I²C Master Interface Port	Conduit	–	`i2c_scl`	Inout	The SCL signal from the I²C bus on the HDMI connector. Note: This signal is not available if you turn off the Include I2C parameter.
	Conduit	–	`i2c_sda`	Inout	The SDA signal from the I²C bus on the HDMI connector. Note: This signal is not available if you turn off the Include I2C parameter.
	Avalon MM	`mgmt_clk`	`i2c_master_address[3:0]`	Input	The Avalon® memory-mapped interface signals to the I²C master. Connect these signals to an Avalon® memory-mapped master such as the Nios® processor to perform read and write operations to the EDID block. Note: These signals are not available if you turn off the Include I2C parameter.
	Avalon MM	`mgmt_clk`	`i2c_master_write`	Input
	Avalon MM	`mgmt_clk`	`i2c_master_read`	Input
	Avalon MM	`mgmt_clk`	`i2c_master_writedata[31:0]`	Input
	Avalon MM	`mgmt_clk`	`i2c_master_readdata[31:0]`	Output
AXI4-Stream Video (Only applicable when Enable Active Video Protocol = AXIS-VVP Full)	AXI4 Stream	`axi4s_clk`	`axi4s_vid_in_tvalid`	Input	AXI4-Stream video interface. The transfer protocol follows AXI4-Stream format (full variant) as indicated in Intel FPGA Streaming Video Protocol Specification. Refer the link in Related Information.
	AXI4 Stream	`axi4s_clk`	`axi4s_vid_in_tready`	Output
	AXI4 Stream	`axi4s_clk`	`axi4s_vid_in_tlast`	Input
	AXI4 Stream	`axi4s_clk`	`axi4s_vid_in_tuser`	Input
	AXI4 Stream	`axi4s_clk`	`axi4s_vid_in_tdata`	Input
AXI4-Stream Auxiliary (Only applicable when Enable Active Video Protocol = AXIS-VVP Full)	AXI4 Stream	`axi4s_clk`	`axi4s_aux_in_tvalid`	Input	AXI4-Stream auxiliary interface. Refer to section TX AXI4-Stream Auxiliary Bridge for the AXI4-Stream auxiliary transfer protocol.
	AXI4 Stream	`axi4s_clk`	`axi4s_ aux _in_tready`	Output
	AXI4 Stream	`axi4s_clk`	`axi4s_ aux _in_tlast`	Input
	AXI4 Stream	`axi4s_clk`	`axi4s_ aux _in_tuser`	Input
	AXI4 Stream	`axi4s_clk`	`axi4s_ aux _in_tdata`	Input
HDMI TX Avalon Memory-Mapped Control (Only applicable when Enable Active Video Protocol = AXIS-VVP Full)	Avalon MM	`mgmt_clk`	`av_mm_control_write`	Input	Avalon memory-mapped interface to access to HDMI TX core Avalon memory-mapped demultiplexer, which provide read or write acess to HDMI I2C master for DDC, HDMI TX registers, AXI4-stream to clocked video registers, HDCP (reserved for future use). The addressing mode for this Avalon Memory-Mapped interface is double-word addressing
	Avalon MM	`mgmt_clk`	`av_mm_control_read`	Input
	Avalon MM	`mgmt_clk`	`av_mm_control_address`	Input
	Avalon MM	`mgmt_clk`	`av_mm_control_writedata`	Output
	Avalon MM	`mgmt_clk`	`av_mm_control_readdata`	Output
	Avalon MM	`mgmt_clk`	`av_mm_control_waitrequest`	Input
	Avalon MM	`mgmt_clk`	`av_mm_control_debugaccess`	Input
	Avalon MM	`mgmt_clk`	`av_mm_control_lock`	Input
	Avalon MM	`mgmt_clk`	`av_mm_control_byteenable`	Input
HDCP Port (Applicable only when you enable Support HDCP 2.3 or Support HDCP 1.4 parameters)	Reset	–	`hdcp_reset`	Input	Main asynchronous reset.
	Clock	–	`csr_clk`	Input	HDCP clock for control and status registers. Typically, shares the Nios II processor clock (100 MHz).
	Clock	–	`crypto_clk`	Input	HDCP 2.3 clock for authentication and cryptographic layer. You can use any clock with a frequency of up to 200 MHz. Not applicable for HDCP 1.4. Note: The clock frequency determines the authentication latency.
	Avalon-MM	`csr_clk`	`csr_addr[7:0]`	Input	The Avalon-MM slave port that provides access to internal control and status register, mainly for authentication messages transfer. This interface is expected to operate at Nios II processor clock domain. Because of the extremely large bit portion of message, the IP transfers the message in burst mode with full handshaking mechanism. Write transfers always have a wait time of 0 cycle while read transfers have a wait time of 1 cycle. The addressing should be accessed as word addressing in the Platform Designer flow. For example, addressing of 4 in the Nios II software selects the address of 1 in the slave.
			`csr_wr`	Input
			`csr_rd`	Input
			`csr_wrdata[31:0]`	Input
			`csr_rddata[31:0]`	Output
	Conduit (Key)	`crypto_clk`	`kmem_wait`	Input	Always keep this signal asserted until the key is ready to be read. This signal is not available if you turn on the Support HDCP Key Management parameter.
			`kmem_rdaddr[3:0]` (HDCP 2.3) `kmem_rdaddr[9:4]` (HDCP 1.4)	Output	Key read address bus. [3:2] = Reserved. This signal is not available if you turn on the Support HDCP Key Management parameter.
			`kmem_q[31:0]` (HDCP 2.3) `kmem_q[87:32]` (HDCP 1.4)	Input	32-bit (HDCP 2.3) or 56-bit (HDCP 1.4) data for read transfers. Read transfer always have a wait time of 1 cycle. This signal is not available if you turn on the Support HDCP Key Management parameter.
	Avalon-MM	`csr_clock`	`hdcp1_kmem_wr`	Input	The Avalon® memory-mapped slave port provides write access to internal HDCP 1.4 key storage. Write transfers always have a wait time of 0 The Avalon® memory-mapped master access the addressing as word addressing in the Platform Designer flow. For example, addressing of 4 in the Avalon® memory-mapped master selects the address of 1 in the slave. These signals are only available if you turn on the Support HDCP Key Management parameter and the Support HDCP 1.4 parameter.
			`hdcp1_kmem_wrdata[31:0]`	Input
			`hdcp1_kmem_addr[6:0]`	Input
	Avalon-MM	`csr_clk`	`hdcp2_kmem_wr`	Input	The Avalon® memory-mapped slave port provides write access to internal HDCP 2.3 key storage. Write transfers always have a wait time of 0 The Avalon® memory-mapped master access the addressing as word addressing in the Platform Designer flow. For example, addressing of 4 in the Avalon® memory-mapped master selects the address of 1 in the slave. These signals are only available if you turn on the Support HDCP Key Management parameter and the Support HDCP 2.3 parameter.
			`hdcp2_kmem_wrdata[31:0]`	Input
			`hdcp2_kmem_addr[3:0]`	Input
	Conduit	`ls_clk`	`hdcp1_enabled`	Output	This signal is asserted by the IP if the outgoing video and auxiliary data are HDCP 1.4 encrypted.
		`ls_clk`	`hdcp2_enabled`	Output	This signal is asserted by the IP if the outgoing video and auxiliary data are HDCP 2.3 encrypted.
		`csr_clk`	`hdcp1_disable`	Input	Assert this signal to disable the HDCP 1.4 IP. Note: You must reset the HDCP IP (`hdcp_reset`) after toggling this signal. You must not call the software API `hdcp_main()` while this signal is asserted. You must call the software API `hdcp_unauth()` after deasserting this signal.
		`csr_clk`	`hdcp2_disable`	Input	Assert this signal to disable the HDCP 2.3 IP. Note: You must reset the HDCP IP (`hdcp_reset`) after toggling this signal. You must not call the software API `hdcp_main()` while this signal is asserted. You must call the software API `hdcp_unauth()` after deasserting this signal.

Table 38. out_c Value for TMDS Bit Rate Less than 3.4 Gbps `TMDS_Bit_clock_Ratio` = 0 and `out_c` value is constant.
N	out_c Value
1	10'b1111100000
2	20'b1111100000_1111100000
4	40'b1111100000_1111100000 1111100000_1111100000

Table 39. out_c Value for TMDS Bit Rate Greater than 3.4 Gbps in TMDS Mode `TMDS_Bit_clock_Ratio` = 1 and `out_c` value is repeated indefinitely.
N	out_c Value
N	t	t+1	t+2	t+3
1	10’h000	10’h000	10’h3ff	10’h3ff
2	20’h00000	20’hfffff	20'h00000	20’hfffff
4	40’hfffff 00000	40’hfffff 00000	40’hfffff 00000	40’hfffff 00000

Table 40. Audio Channels
Bit-Field	Audio Channel
Bit-Field	LPCM and 3D Audio (LPCM)	MST Audio (LPCM)
255:224	8 or 16 or 24 or 32	Stream 4 right channel
223:192	7 or 15 or 23 or 31	Stream 4 left channel
191:160	6 or 14 or 22 or 30	Stream 3 right channel
159:128	5 or 13 or 21 or 29	Stream 3 left channel
127:96	4 or 12 or 20 or 28	Stream 2 right channel
95:64	3 or 11 or 19 or 27	Stream 2 left channel
63:32	2 or 10 or 18 or 26	Stream 1 right channel
31:0	1 or 9 or 17 or 25	Stream 1 left channel

⁵

aux_clk = ls_clk (Support FRL = 0)

aux_clk = vid_clk (Support FRL = 1)

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5.2. Source Interfaces