HDMI Intel® FPGA IP User Guide

ID 683798
Date 4/10/2023
Public

A newer version of this document is available. Customers should click here to go to the newest version.

Document Table of Contents

9.1.1.3. IRQ_MASK (0x02)

Table 68.  IRQ_MASK (0x02)
Name Bit(s) Access Description Reset
Reserved 31:4 - - -
Video overflow mask 3 RW Mask the video overflow input interrupt 0x0
Hotplugdetect mask 2 RW Mask the hotplug detect (HPD) input interrupt 0x0
Reserved 1:0 - - -