HDMI Intel® FPGA IP User Guide

ID 683798
Date 12/15/2021

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Document Table of Contents Sink Display Data Channel (DDC) & Status and Control Data Channel (SCDC)

The HDMI source uses the DDC to determine the capabilities and characteristics of the sink by reading the Enhanced Extended Display Identification Data (E-EDID) data structure.

The E-EDID memory is stored using the RAM 1-Port IP core. A standard two-wire (clock and data) serial data bus protocol (I2C slave-only controller) is used to transfer CEA-861-D compliant E-EDID data structure.

The 8-bit I2C slave addresses for the E-EDID are 0xA0/0xA1. The LSB indicates the access type: 1 for read and 0 for write. When an HPD event occurs, the I2C slave responds to E-EDID data by reading from the RAM.

The I2C slave-only controller is also used to support SCDC for HDMI 2.0b operation. The 8-bit I2C slave addresses for the SCDC are 0xA8/0xA9. When an HPD event occurs, the I2C slave performs write/read transaction to/from SCDC interface of HDMI RX core. This I2C slave-only controller for SCDC is not required if HDMI 2.0b is not intended.