HDMI Intel® FPGA IP User Guide

ID 683798
Date 12/15/2021

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Document Table of Contents

8. HDMI Simulation Example

The HDMI simulation example evaluates the functionality of the HDMI Intel® FPGA IP and provides a starting point for you to create your own simulation.
This simulation example targets the ModelSim* - Intel® FPGA Starter Edition simulator. The simulation covers the following core features:
  • IEC-60958 audio format
  • Standard H/V/DE/RGB input video format
  • Support for HDMI 2.0b scrambled operation
Note: This simulation flow applies only for the Intel® Quartus® Prime Standard Edition software using ModelSim* - Intel® FPGA Starter Edition. For the Intel® Quartus® Prime Pro Edition simulation flow, refer to the respective design example user guides.
Figure 67. HDMI Testbench

The Test Pattern Generator (TPG) provides the video stimulus. The IP core stimulates the HDMI TX core using an audio packet generator and aux packet generator. The output from the HDMI TX core drives the HDMI RX core.

The IP core requires a memory-mapped master stimulus to operate the testbench for HDMI 2.0b scrambling. This stimulus implements the activity normally seen across the I2C DDC channel. At this point, the IP core asserts the scramble enable bit in the SCDC registers.

The testbench implements CRC checking on the input and output video. The testbench checks the CRC value of the transmitted data against the CRC calculated in the received video data. The testbench performs the checking after detecting 4 stable V-SYNC signals from the receiver.

The aux sample generator generates a fixed data to be transmitted from the transmitter. On the receiver side, the generator compares whether the expected aux data is received and decoded correctly.

The audio sample generator generates an incrementing test data pattern to be transmitted through the audio channel. On the receiver side, the audio data checker checks and compares whether the incrementing test data pattern is received and decoded correctly.