Multi Channel DMA Intel® FPGA IP for PCI Express* Release Notes

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ID 683791
Date 11/04/2024
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1. Multi Channel DMA Intel® FPGA IP for PCI Express : IP Release Notes
1. Multi Channel DMA Intel® FPGA IP for PCI Express : IP Release Notes x
1.1. Multi Channel DMA Intel® FPGA IP for PCI Express* : IP Core [H-Tile: 24.2.0] [P-Tile: 8.2.0] [F-Tile: 9.2.0] [R-Tile: 5.2.0] 1.2. Multi Channel DMA Intel® FPGA IP for PCI Express* : IP Core [H-Tile: 24.1.0] [P-Tile: 8.1.0] [F-Tile: 9.1.0] [R-Tile: 5.1.0] 1.3. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 23.1.0] [P-Tile: 7.1.0] [F-Tile: 8.0.0] [R-Tile: 4.1.0] 1.4. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 23.0.0] [P-Tile: 7.0.0] [F-Tile: 7.0.0] [R-Tile: 4.0.0] 1.5. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.3.0] [P-Tile: 6.0.0] [F-Tile: 6.0.0] [R-Tile: 3.0.0] 1.6. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.2.0] [P-Tile: 5.1.0] [F-Tile: 5.1.0] [R-Tile: 2.0.0] 1.7. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.1.0] [P-Tile: 5.0.0] [F-Tile: 5.0.0] [R-Tile: 1.0.0] 1.8. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.0.0] [P-Tile: 4.0.0] [F-Tile: 4.0.0] 1.9. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.5.0 ] [P-Tile: 3.1.0 ] [F-Tile: 3.0.0 ] 1.10. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.4.0 ] [P-Tile: 3.0.0] [F-Tile: 2.0.0] 1.11. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.3.0] [P-Tile: 2.2.0] [F-Tile: 1.1.0] 1.12. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.2.0] [P-Tile: 2.1.0] [F-Tile: 1.0.0] 1.13. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [P-Tile: v2.0.0] [H-Tile: v21.1.0] 1.14. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [P-Tile: v1.0.0] [H-Tile: v2.0.0] 1.15. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core v20.0.0 1.16. Multi Channel DMA Intel FPGA IP for PCI Express : User Guide Archives
1. Multi Channel DMA Intel® FPGA IP for PCI Express : IP Release Notes

1.8. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.0.0] [P-Tile: 4.0.0] [F-Tile: 4.0.0]

Table 8.  Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.0.0] [P-Tile: 4.0.0] [F-Tile: 4.0.0] : 2022.10.11
Quartus® Prime Version IP Version Description Impact
22.3

[H-Tile: 22.0.0]

[P-Tile: 4.0.0]

[F-Tile: 4.0.0]

Added support for Root Port Address Translation Table in BAS and BAM+BAS modes (MCDMA P and F Tiles)

You can use ATT to access 64-bit PCIe address space.

Added support for Endpoint MSI request interface in BAS and BAM+BAS modes (MCDMA P and F Tiles)

You can use MSI request interface to trigger MSI messages.

Added support for 2x8 bifurcation mode (MCDMA P and F Tiles)

You can instantiate two separate instances of MCDMA IP Core in x8 mode

Added support for 64-byte non-aligned support for NetDev

With Enable address byte aligned transfer checked, this enables byte aligned data transfer in AVST H2D direction.

Enhanced Packet Generator/Checker example design to support the Channel and Function ID information

Supported in Custom and DPDK based MCDMA drivers.

Added support for D2H Data Mover Data Drop feature

Supported in Custom and DPDK based MCDMA drivers.
Added the following new Hard IP Modes and PLD clock frequencies support:
  • Gen4 1x16 Interface - 512 bit (PLD Clock Frequency 175 MHz / 200 MHz / 225 MHz / 250 MHz)
  • Gen4 2x8 Interface - 256 bit (PLD Clock Frequency 175 MHz / 200 MHz / 225 MHz / 250 MHz)
  • Gen3 2x8 Interface - 256 bit (PLD Clock Frequency 250 MHz)

PCIe port bifurcation is now supported by MCDMA IP for P-Tile and F-Tile. IT allows users to implement two PCIe links with MCDMA IP on a single tile.

Lower PLD clock frequency options are provided to ease timing closure when the throughput of the PCIe link can be a trade off.

Added Intel Agilex F-Series F-Tile ES FPGA Development Kit board preset for design example generation.

The VID-related settings including the pin assignments are included in the .qsf file of the generated design example when selected.

Added Eye Viewer feature in F-Tile Debug Toolkit while in Endpoint mode and using Linux OS and Windows.

Allows users to measure on-die eye height margin.
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