1.7. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 22.1.0] [P-Tile: 5.0.0] [F-Tile: 5.0.0] [R-Tile: 1.0.0]
Quartus® Prime Version | IP Version | Description | Impact |
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22.4 | [H-Tile: 22.1.0] [P-Tile: 5.0.0] [F-Tile: 5.0.0] [R-Tile: 1.0.0] |
The default User Mode parameter on m1 instance fixed when Root Port Mode is selected. |
Users can implement MCDMA IP in Root Port Mode. |
Fixed the MCDMA P-Tile BAM performance issue when BAM+BAS Mode and Traffic Generator/Checker Design Example is compiled. |
Hardware is capable to reach expected performance. |
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Initial release of MCDMA R-Tile IP Core. Added support for R-Tile Gen5 x8, Gen4/Gen3 x16 and Gen4/Gen3 x8 (Root Port,Endpoint). MCDMA R-Tile Hardware support is available in Quartus® Prime 22.4 Release Patch 0.02. |
Users can implement up to Gen5 x8 link in the Agilex™ 7 FPGA devices using R-Tile. |
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Added support for BAM-BAS-MCDMA (EP) user mode, for MCDMA H-Tile, P-Tile and F-Tile IP Cores. |
Users can now use BAM, BAS and MCDMA modes simultaneously in Endpoint mode applications. |
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R-Tile MCDMA Design Example simulations are not supported in this Quartus® Prime release. |
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MCDMA R-Tile MSI, simultaneous BAM+BAS+MCDMA and Root Port ATT features in the Quartus® Prime GUI are not supported |
Support for these features may be added in a future Quartus® Prime release. |
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Removed pld_clrpcs_n_i input from MCDMA P-Tile IP Core. New reset signals (p#_warm_perst_n_i, p#_cold_perst_n_i) are exported to the top-level block symbol when independent resets are enabled. |
IP Upgrade tool does not upgrade automatically and requires manual upgrade (Upgrade in Editor). If pld_clrpcs_n_i reset was used by application logic, switch to new reset signals input before manual upgrade. |
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Removed support for kernel mode Char driver. |
Users can use netdev (kernel mode) driver and custom and DPDK (user mode) driver. |
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Added support for Independent cold and warm reset operations for the ports in the x8x8 Endpoint in F-Tile. |
New reset signals (i_gpio_perst#_n) are exported to the top-level block symbol when independent resets are enabled. |