1.1. Multi Channel DMA IP for PCI Express* : IP Core [H-Tile: v24.2.2] [P-Tile: v8.3.2] [F-Tile: v9.3.2] [R-Tile: v5.3.2]
1.2. Multi Channel DMA IP for PCI Express* : IP Core [H-Tile: v24.2.1] [P-Tile: v8.3.1] [F-Tile: v9.3.1] [R-Tile: v5.3.1]
1.3. Multi Channel DMA IP for PCI Express* : IP Core [H-Tile: v24.2.0] [P-Tile: v8.3.0] [F-Tile: v9.3.0] [R-Tile: v5.3.0]
1.4. Multi Channel DMA IP for PCI Express* : IP Core [H-Tile: v24.2.0] [P-Tile: v8.2.0] [F-Tile: v9.2.0] [R-Tile: v5.2.0]
1.5. Multi Channel DMA IP for PCI Express* : IP Core [H-Tile: v24.1.0] [P-Tile: v8.1.0] [F-Tile: v9.1.0] [R-Tile: v5.1.0]
1.6. Multi Channel DMA IP for PCI Express : IP Core [H-Tile: v23.1.0] [P-Tile: v7.1.0] [F-Tile: v8.0.0] [R-Tile: v4.1.0]
1.7. Multi Channel DMA IP for PCI Express : IP Core [H-Tile: v23.0.0] [P-Tile: v7.0.0] [F-Tile: v7.0.0] [R-Tile: v4.0.0]
1.8. Multi Channel DMA IP for PCI Express : IP Core [H-Tile: v22.3.0] [P-Tile: v6.0.0] [F-Tile: v6.0.0] [R-Tile: v3.0.0]
1.9. Multi Channel DMA IP for PCI Express : IP Core [H-Tile: v22.2.0] [P-Tile: v5.1.0] [F-Tile: v5.1.0] [R-Tile: v2.0.0]
1.10. Multi Channel DMA IP for PCI Express : IP Core [H-Tile: v22.1.0] [P-Tile: v5.0.0] [F-Tile: v5.0.0] [R-Tile: v1.0.0]
1.11. Multi Channel DMA IP for PCI Express : IP Core [H-Tile: v22.0.0] [P-Tile: v4.0.0] [F-Tile: v4.0.0]
1.12. Multi Channel DMA IP for PCI Express : IP Core [H-Tile: v21.5.0 ] [P-Tile: v3.1.0 ] [F-Tile: v3.0.0 ]
1.13. Multi Channel DMA IP for PCI Express : IP Core [H-Tile: v21.4.0 ] [P-Tile: v3.0.0] [F-Tile: v2.0.0]
1.14. Multi Channel DMA IP for PCI Express : IP Core [H-Tile: v21.3.0] [P-Tile: v2.2.0] [F-Tile: v1.1.0]
1.15. Multi Channel DMA IP for PCI Express : IP Core [H-Tile: v21.2.0] [P-Tile: v2.1.0] [F-Tile: v1.0.0]
1.16. Multi Channel DMA IP for PCI Express : IP Core [P-Tile: v2.0.0] [H-Tile: v21.1.0]
1.17. Multi Channel DMA IP for PCI Express : IP Core [P-Tile: v1.0.0] [H-Tile: v2.0.0]
1.18. Multi Channel DMA IP for PCI Express : IP Core v20.0.0
1.19. Multi Channel DMA IP for PCI Express : User Guide Archives
1.16. Multi Channel DMA IP for PCI Express : IP Core [P-Tile: v2.0.0] [H-Tile: v21.1.0]
Quartus® Prime Version | Description | Impact |
---|---|---|
21.2 | Fixed H-Tile IP revision number |
Enables automatic upgrade by Quartus® Prime Pro Edition software |
Added 500 MHz support for Agilex™ 7 P-Tile MCDMA IP |
Provides maximum Gen4 link bandwidth |
|
Added P-Tile single port Avalon-ST DMA up to 256 channels |
Enables efficient DMA bandwidth sharing and utilization |
|
Added MCDMA IP Kernel Mode (No SRIOV) driver |
You can perform DMA operations to and from memory buffer allocated in user space using chardev system calls (open, close, poll, read, write, etc) |
|
Fixed port width of MCDMA P-Tile usr_hip_tl_cfg_func_o and usr_hip_tl_cfg_ctl_o:
|
You need to adjust application logic port width according to the IP port width if these ports are used in your application. |