Multi Channel DMA Intel® FPGA IP for PCI Express Release Notes

ID 683791
Date 12/27/2022
Public

1.5. Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.3.0] [P-Tile: 2.2.0] [F-Tile: 1.1.0]

Table 5.  Multi Channel DMA Intel FPGA IP for PCI Express : IP Core [H-Tile: 21.3.0] [P-Tile: 2.2.0] [F-Tile: 1.1.0] : 2022.01.14
Intel® Quartus® Prime Version IP Version Description Impact
21.4

[H-Tile: 21.3.0]

[P-Tile: 2.2.0]

[F-Tile: 1.1.0]

Multi-channel support in netdev

Currently supports 512 channels in each PF

SRIOV support in netdev

You can enable multiple VFs by using sysfs interface

ethtool enhancements

Queue management and Ring management support enabled from ethtool command

Added a new MCDMA user mode, the Data Mover Only mode, for MCDMA P-Tile and F-Tile IP Cores.

You can attach external/custom descriptor controller.

Added 10-bit tag support

Enables MCDMA to support greater than 256 outstanding Non-Posted Requests

Simulation bug fix for:
  • BAM user mode : PIO using MQDMA Bypass mode design example variant.
  • MCDMA+BAM : PIO using MQDMA Bypass mode design example variant.
  • BAM+BAS user mode : Traffic Generator/Checker design example variant.

Allows you to simulate the design examples with the supported simulator.

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