Multi Channel DMA Intel® FPGA IP for PCI Express Release Notes

ID 683791
Date 12/27/2022

1.2. Multi Channel DMA for PCI Express Intel FPGA IP : IP Core [P-Tile: v2.0.0] [H-Tile: v21.1.0]

Table 2.  Multi Channel DMA for PCI Express Intel FPGA IP : IP Core [P-Tile: 2.0.0] [H-Tile: 21.1.0] 2021.09.29
Intel® Quartus® Prime Version IP Version Description Impact

[P-Tile: v2.0.0]

[H-Tile: v21.1.0]

Fixed H-Tile IP revision number

Enables automatic upgrade by Intel® Quartus® Prime Pro Edition software

Added 500 MHz support for Intel® Agilex™ P-Tile MCDMA IP

Provides maximum Gen4 link bandwidth

Added P-Tile single port Avalon-ST DMA up to 256 channels

Enables efficient DMA bandwidth sharing and utilization

Added MCDMA IP Kernel Mode (No SRIOV) driver

You can perform DMA operations to and from memory buffer allocated in user space using chardev system calls (open, close, poll, read, write, etc)

Fixed port width of MCDMA P-Tile usr_hip_tl_cfg_func_o and usr_hip_tl_cfg_ctl_o:
  • usr_hip_tl_cfg_func_o [1:0] --> usr_hip_tl_cfg_func_o [2:0]
  • usr_hip_tl_cfg_ctl_o [31:0] --> usr_hip_tl_cfg_ctl_o [15:0]

You need to adjust application logic port width according to the IP port width if these ports are used in your application.

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