1. Overview 2. CvP Description 3. CvP Topologies 4. Design Considerations 5. CvP Driver and Registers 6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Devices 7. Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide Archives 8. Document Revision History for the Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide
5.3.1. Vendor Specific Capability Header Register 5.3.2. Vendor Specific Header Register 5.3.3. Intel® Marker Register 5.3.4. User Configurable Device/Board ID Register 5.3.5. CvP Status Register 5.3.6. CvP Mode Control Register 5.3.7. CvP Data Registers 5.3.8. CvP Programming Control Register 5.3.9. CvP Credit Register
- 6.1.1. Generating the Synthesis HDL files for Intel® FPGA P-Tile Avalon Streaming (Avalon-ST) for PCIe* Express
18.104.22.168. Programming CvP Images
In Active Serial configuration mode, you must program the periphery image (.periph.jic) into your AS configuration device and then download the core image (.core.rbf) using the PCIe Link. You can use Active Serial x4 (Fast mode) to load .periph.jic into your selected CvP initialization enabled Intel® Agilex™ device.
After loading the periphery image, the Intel® Agilex™ device is triggered to reconfigure from AS to load it. The link should reach the expected data rate and link width. You can confirm the PCIe link status using the RW Utilities. Follow these steps to program and test the CvP functionality:
- Plug the Intel® Agilex™ device PCIe* card into the PCI Express slot of the DUT PC and power it ON.
- Open the Intel® Quartus® Prime Tools menu and select Programmer.
- Click Auto Detect to verify that the Intel® FPGA Download Cable recognizes the Intel® Agilex™ device.
- Follow these steps to program the periphery image:
- Select Intel® Agilex™ device, and then right click None under File column and select Change File.
- Navigate to .periph.jic file and click Open.
- Under Program/Configure column, select the respective devices.
- Click Start to program the periphery image into flash.
- After the .periph.jic is programmed, the FPGA must be powered cycle to allow the new peripheral image to load from the on-board flash into the FPGA. To force the DUT PC to re-enumerate the link with the new image, power cycle the DUT PC and the Intel® Agilex™ device PCIe* card.
- You can use RW Utilities or another system software driver to verify the link status. You can also confirm expected link speed and width.
- Follow these steps to program the core image via PCIe link:
- Copy the .core.rbf file into /lib/firmware
- In the /lib/firmware directory, run the following command to use the FPGA manager to configure the core image.
- Run: su to get root access.
echo <filename>.core.rbf > /sys/kernel/debug/fpga_manager/fpga0/firmware_name
- You can see your core image running on the Intel® Agilex™ device PCIe* card. Alternatively, print out the kernel message using the dmesg to ensure the CvP is completed successfully.
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