- 6.1.1. Generating the Synthesis HDL files for Intel® FPGA P-Tile Avalon Streaming (Avalon-ST) for PCIe* Express
2.2.1. CvP Initialization Mode
In this mode, an external configuration device stores the periphery image and it loads into the FPGA through the Active Serial x4 (Fast mode) configuration scheme. The host memory stores the core image and it loads into the FPGA through the PCIe* link. The PCIe* REFCLK needs to be running prior to sending the periphery image.
To configure the periphery image while meeting the 100ms of link up requirement for , you must specify the OSC_CLK_1 pin as 25MHz, 100MHz, or 125MHz, and set the AS_CLK clock to 166 MHz.
After the periphery image configuration is complete, the CONF_DONE signal goes high and the FPGA starts PCIe* link training. When PCIe* link training is complete, the PCIe* link transitions to L0 state and then allows the host to complete PCIe* enumeration of the link. The PCIe* host then initiates the core image configuration through the PCIe* link.
After the core image configuration is complete, the CVP_CONFDONE pin (if enabled) goes high, indicating the FPGA is fully configured.
After the FPGA is fully configured, the FPGA enters user mode. If the INIT_DONE signal is enabled, the INIT_DONE signal goes high after initialization is complete and the FPGA enters user mode.
In user mode, the PCIe* links are available for normal PCIe* applications.
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