1. Overview 2. CvP Description 3. CvP Topologies 4. Design Considerations 5. CvP Driver and Registers 6. Understanding the Design Steps for CvP Initialization using the Supported PCIe Tile in Devices 7. Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide Archives 8. Document Revision History for the Intel® Agilex™ Device Configuration via Protocol (CvP) Implementation User Guide
5.3.1. Vendor Specific Capability Header Register 5.3.2. Vendor Specific Header Register 5.3.3. Intel® Marker Register 5.3.4. User Configurable Device/Board ID Register 5.3.5. CvP Status Register 5.3.6. CvP Mode Control Register 5.3.7. CvP Data Registers 5.3.8. CvP Programming Control Register 5.3.9. CvP Credit Register
- 6.1.1. Generating the Synthesis HDL files for Intel® FPGA P-Tile Avalon Streaming (Avalon-ST) for PCIe* Express
6.1. Implementation of CvP Initialization Mode
CvP Initialization mode splits the bitstream into periphery and core images. The periphery image is stored in a local flash device on the PCB. The core image is stored in host memory. You must download the core image to the FPGA using the PCI Express link.
You must specify CvP Initialization mode in the Intel® Quartus® Prime Pro Edition software by selecting the CvP Settings Initialization and Update and you must also instantiate the PCI Express IP core.
Note: The P-Tile Avalon Memory Mapped IP is not available in the IP Catalog from Intel® Quartus® Prime version 21.2 onwards. The replacement IP is the MCDMA-based PCI Express Avalon Memory Mapped IP.
Figure 8. Example Implementation Flow for CvP Initialization
The CvP Initialization demonstration walkthrough includes the following steps:
Generating the Synthesis HDL files for Intel FPGA P-Tile Avalon Streaming (Avalon-ST) for PCIe Express
Setting up the CvP Parameters in Device and Pin Options
Compiling the Design
Converting the SOF File
Bringing up the Hardware
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