Video and Image Processing Suite Release Notes

ID 683726
Date 4/15/2019

1.2. Video and Image Processing Suite v18.1

Table 2.  v18.1 September 2018
Description Impact

Added new registers for the Deinterlacer II Intel FPGA IP.

  • Added new run-time control and status registers to improve deinterlacing quality for mid-range motion-adaptive configurations.
  • Added new registers to allow run-time switching between “bob”, ”weave” and “motion adaptive” modes.
These changes are optional. If you do not upgrade your IP core, it does not have these new features.

Added new GUI parameters for the Mixer II Intel FPGA IP.

  • Synchronize background to layer 0
  • InputN alpha channel
  • Reduced control register readback
  • Add extra register stages to data pipeline

Added new test pattern options for the Test Pattern II Intel FPGA IP.