1.6. Video and Image Processing Suite v16.1

Video and Image Processing Suite Release Notes

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ID 683726

Date 4/15/2019

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Ixiasoft

1.6. Video and Image Processing Suite v16.1

Table 6. v16.1 October 2016
Description	Impact
Added the following new IP cores for 16.1 release: 2D FIR Filter II Chroma Resampler II Color Plane Sequencer II Gamma Corrector II Interlacer II All these IP cores support pixels in parallel and run-time control.	These changes are optional. If you do not upgrade your IP core, it does not have these new features.
Removed the Broadcast Deinterlacer IP core and merged the features into the Deinterlacer II IP core. If you were using the Broadcast Deinterlacer IP core versions 15.1 or 16.0, Qsys will automatically upgrade your design to the Deinterlacer II version 16.1 with the same configuration.
Mixer II IP core Updated alpha stream information for Mixer II IP core. When you enable alpha stream, the LSB is in Alpha value and the control packets are composed of all symbols including Alpha.
Clocked Video Interface IP core Added new parameters for Clocked Video Input II IP core: Enable matching data packet to control by clipping: Turning on this parameter clips the input video frame to match the resolution sent in control packet. Enable matching data packet to control by padding: Turning on this parameter pads the incoming frame if it is smaller and/or shorter than the resolution specified in the control packet. Overflow handling: Turning on this parameter ends the current frame (with dummy pixel data) based on the resolution specified in the control packet if overflow happens. Added new signals Clocked Video Input II IP core: `Clipping` and `Padding`. Updated information about the `Status` register Clocked Video Input II IP core to include bits to support clipping and padding features. Added new parameter for Clocked Video Output II IP core: Low latency mode: Setting this parameter to 1 enables the IP core to start timing for a new frame immediately.