Video and Image Processing Suite Release Notes

ID 683726
Date 4/15/2019
Public

1.9. Video and Image Processing Suite v15.0

Table 9.  v15.0 May 2015
Description Impact
Updated the Input (0-3) Enable registers for the Mixer II IP core. The 1-bit registers are changed to 2-bit registers:
  • Set to bit 0 of the registers to display input 0.
  • Set to bit 1 of the registers to enable consume mode.
These changes are optional. If you do not upgrade your IP core, it does not have these new features.
Updated the parameter settings for the Mixer II IP core.
  • Added a new parameter Pattern which enables you to select the pattern for the background layer.
  • Removed Color planes transmitted in parallel . This feature is now default and internally handled through the hardware TCL file.
Updated the parameter settings for the Frame Buffer II IP core.
  • Added support for the following parameters (these were not supported in the previous version): Maximum ancillary packets per frame, Interlace support, Locked rate support, Run-time writer control, andRun-time reader control
  • Removed Ready latency and Delay length (frames). These features are fixed to 1 and internally handled through the hardware TCL file.
Updated the parameter settings for the Avalon-ST Video Monitor IP core.
  • Added new parameters: Color planes transmitted in parallel and Pixels in parallel.
  • Removed Number of color planes in sequence. You can specify whether to transmit the planes in parallel or in series using the Color planes transmitted in parallel parameter.