Intel® FPGA Programmable Acceleration Card N3000 Board Management Controller User Guide

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ID 683709
Date 11/25/2019
Public
Document Table of Contents
Document Table of Contents x
1. Intel FPGA Programmable Acceleration Card N3000 BMC Introduction 2. Board Monitoring through PLDM over MCTP SMBus 3. Board Monitoring through I2C SMBus 4. EEPROM Data Format 5. Revision History
1. Intel FPGA Programmable Acceleration Card N3000 BMC Introduction x
1.1. About this Document 1.2. Overview 1.3. Root of Trust (RoT) 1.4. Secure Remote System Update 1.5. Power Sequence Management 1.6. Board Monitoring Through Sensors
2. Board Monitoring through PLDM over MCTP SMBus x
2.1. SMBus Interface Speed 2.2. MCTP Packetization Support 2.3. Supported Command Sets 2.4. PLDM Topology and Hierarchy
4. EEPROM Data Format x
4.1. MAC EEPROM 4.2. Field Replaceable Unit Identification (FRUID) EEPROM Access
1. Intel FPGA Programmable Acceleration Card N3000 BMC Introduction
2. Board Monitoring through PLDM over MCTP SMBus
3. Board Monitoring through I2C SMBus
4. EEPROM Data Format
5. Revision History

1.5. Power Sequence Management

The BMC Power sequencer state machine manages Intel® FPGA PAC N3000 power-on and power-off sequences for corner cases during the power-on process or normal operation. The Intel® MAX® 10 power-up flow covers the entire process including Intel® MAX® 10 boot-up, Nios® boot-up, and power sequence management for FPGA configuration. The host must check the build versions of both the Intel® MAX® 10 and FPGA, as well as the Nios® status after every power-cycle, and take corresponding actions in case the Intel® FPGA PAC N3000 runs into corner cases such as a Intel® MAX® 10 or FPGA factory build load failure or Nios® boot up failure. The BMC protects the Intel® FPGA PAC N3000 by shutting down power to the card under the following conditions:
  • 12 V Auxiliary or PCIe edge supply voltage is below 10.46 V
  • FPGA core temperature reaches 100°C
  • Board temperature reaches 85 °C
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