Intel® FPGA Programmable Acceleration Card N3000 Board Management Controller User Guide

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ID 683709
Date 11/25/2019
Public
Document Table of Contents
Document Table of Contents x
1. Intel FPGA Programmable Acceleration Card N3000 BMC Introduction 2. Board Monitoring through PLDM over MCTP SMBus 3. Board Monitoring through I2C SMBus 4. EEPROM Data Format 5. Revision History
1. Intel FPGA Programmable Acceleration Card N3000 BMC Introduction x
1.1. About this Document 1.2. Overview 1.3. Root of Trust (RoT) 1.4. Secure Remote System Update 1.5. Power Sequence Management 1.6. Board Monitoring Through Sensors
2. Board Monitoring through PLDM over MCTP SMBus x
2.1. SMBus Interface Speed 2.2. MCTP Packetization Support 2.3. Supported Command Sets 2.4. PLDM Topology and Hierarchy
4. EEPROM Data Format x
4.1. MAC EEPROM 4.2. Field Replaceable Unit Identification (FRUID) EEPROM Access
1. Intel FPGA Programmable Acceleration Card N3000 BMC Introduction
2. Board Monitoring through PLDM over MCTP SMBus
3. Board Monitoring through I2C SMBus
4. EEPROM Data Format
5. Revision History

1.2. Overview

The Intel® MAX® 10 BMC is responsible for controlling, monitoring and granting access to board features. The Intel® MAX® 10 BMC interfaces with on-board sensors, the FPGA and the flash, and manages power-on/power-off sequences, FPGA configuration and telemetry data polling. You can communicate with the BMC using the Platform Level Data Model (PLDM) version 1.1.1 protocol. The BMC firmware is field upgradeable over PCIe using the remote system update feature.

Features of BMC

  • Acts as a Root of Trust (RoT) and enables the secure update features of the Intel® FPGA PAC N3000.
  • Controls firmware and FPGA flash updates over PCIe.
  • Manages FPGA configuration.
  • Configures the network settings for the C827 Ethernet re-timer device.
  • Controls Power up and power down sequencing and fault detection with automatic shut-down protection.
  • Controls power and resets on the board.
  • Interfaces with sensors, FPGA flash and QSFPs.
  • Monitors telemetry data (board temperature, voltage and current) and provides protective action when readings are outside of critical threshold.
    • Reports telemetry data to host BMC via Platform Level Data Model (PLDM) over MCTP SMBus or I2C.
    • Supports PLDM over MCTP SMBus via PCIe SMBus. 0xCE is a 8-bit slave address.
    • Supports I2C SMBus. 0xBC is the 8-bit slave address.
  • Accesses the Ethernet MAC addresses in EEPROM and field replaceable unit identificiation (FRUID) EEPROM.
Figure 1. BMC High-Level Block Diagram
Level Two Title