eCPRI Intel® FPGA IP User Guide

Download PDF
ID 683685
Date 2/22/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Getting Started 3. IP Parameters 4. Functional Description 5. Interface Overview 6. IP Registers 7. eCPRI Intel FPGA IP User Guide Archives 8. Document Revision History for eCPRI Intel® FPGA IP User Guide
1. Introduction x
1.1. Supported Features 1.2. Device Family Support 1.3. eCPRI Intel® FPGA IP Device Speed Grade Support 1.4. Resource Utilization 1.5. Intel® FPGA IP Core Verification 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. Simulating the IP Core 2.5. Compiling the Full Design and Programming the FPGA
2.2. Specifying the IP Core Parameters and Options x
2.2.1. Reference and System PLL Clock for your IP Design
4. Functional Description x
4.1. Interfaces 4.2. High Level Data Path Flow 4.3. Operation of the eCPRI IP Blocks
4.2. High Level Data Path Flow x
4.2.1. Transmit TX Path 4.2.2. Receive RX Path 4.2.3. Supported Ethernet Variants
4.3. Operation of the eCPRI IP Blocks x
4.3.1. Packet Classifier 4.3.2. Ethernet Header Insertion/Removal 4.3.3. Concatenation/De-concatenation 4.3.4. Header Mapper/De-Mapper 4.3.5. eCPRI IWF Type 0 4.3.6. eCPRI Message 5 Packet Parser 4.3.7. Packet Queue 4.3.8. eCPRI Message Type 4.3.9. Error Handling 4.3.10. RX Throttling
4.3.8. eCPRI Message Type x
4.3.8.1. eCPRI Message Type 0- IQ Data Transfer 4.3.8.2. eCPRI Message Type 1- Bit Sequence Transfer 4.3.8.3. eCPRI Message Type 2- Real Time Control Data 4.3.8.4. eCPRI Message Type 3- Generic Data Transfer 4.3.8.5. eCPRI Message Type 4- Remote Memory Access 4.3.8.6. eCPRI Message Type 5- One-Way Delay Measurement 4.3.8.7. eCPRI Message Type 6- Remote Reset 4.3.8.8. eCPRI Message Type 7- Event Indication 4.3.8.9. eCPRI Message Type 64- 255 Vendor Specific
5. Interface Overview x
5.1. Clock Signals 5.2. Power, Reset, and Firewalls Signals 5.3. TX Time of Day Interface 5.4. RX Time of Day Interface 5.5. Interrupt 5.6. Configuration Avalon® Memory-Mapped Interface 5.7. Ethernet MAC Source Interface 5.8. Ethernet MAC Sink Interface 5.9. External ST Source Interface 5.10. External ST Sink Interface 5.11. eCPRI IP Source Interface 5.12. eCPRI IP Sink Interface 5.13. Miscellaneous Interface Signals 5.14. IWF Type 0 eCPRI Interface 5.15. IWF Type 0 CPRI MAC Interface
5.2. Power, Reset, and Firewalls Signals x
5.2.1. Reset Control and Initialization Flows
5.7. Ethernet MAC Source Interface x
5.7.1. E-tile Hard IP for Ethernet 1588 PTP Signals 5.7.2. 25G Ethernet MAC 1588 PTP Signals 5.7.3. 10G Ethernet MAC 1588 PTP Signals
5.14. IWF Type 0 eCPRI Interface x
5.14.1. IWF Source Interface 5.14.2. IWF Sink Interface
5.15. IWF Type 0 CPRI MAC Interface x
5.15.1. CPRI 32-bit IQ Data TX Interface 5.15.2. CPRI 64-bit IQ Data TX Interface 5.15.3. CPRI 32-bit Ctrl_AxC TX Interface 5.15.4. CPRI 64-bit Ctrl_AxC TX Interface 5.15.5. CPRI 32-bit Vendor Specific TX Interface 5.15.6. CPRI 64-bit Vendor Specific TX Interface 5.15.7. CPRI 32-bit Real-time Vendor Specific TX Interface 5.15.8. CPRI 64-bit Real-time Vendor Specific TX Interface 5.15.9. CPRI Gigabit Media Independent Interface (GMII) 5.15.10. CPRI IP L1 Control and Status Interface
1. Introduction
2. Getting Started
3. IP Parameters
4. Functional Description
5. Interface Overview
6. IP Registers
7. eCPRI Intel FPGA IP User Guide Archives
8. Document Revision History for eCPRI Intel® FPGA IP User Guide

5.14.2. IWF Sink Interface

Table 46.  Signals of the IWF Sink InterfaceAll signals are synchronous to clk_rx.
Signal Name Width (Bits) I/O Direction Description
iwf_avst_sink_valid 1 Input Avalon® sink valid from eCPRI IP to client logic.
iwf_avst_sink_data DATA_WIDTH 11 Input Avalon® sink write data from eCPRI IP to client logic.
iwf_avst_sink_sop 1 Input Avalon® sink start of packet from eCPRI IP to client logic. Indicate the beginning of packet.
iwf_avst_sink_eop 1 Input Avalon® sink end of packet from eCPRI IP to client logic. Indicates the end of packet.
iwf_avst_sink_empty LOG2(DATA_WIDTH11/8) Input Avalon® sink empty from eCPRI IP to client logic. . Indicates the number of symbols that are empty, that is, do not represent valid data.
iwf_avst_sink_ready 1 Output Avalon® sink ready driven from eCPRI. Indicates eCPRI can accept data.
iwf_avst_sink_error 1 Input Avalon® sink error from eCPRI IP to client logic. A bit mask to mark errors affecting the data being transferred in the current cycle.
Sideband
iwf_sink_pc_id 16 Input Physical channel ID of the eCPRI message. Lower byte maps to CPRI channel.

Valid on SOP assertion and stable until EOP assertion.

iwf_sink_seq_id 16 Input Sequence ID of the eCPRI message.

Valid on SOP assertion and stable until EOP assertion.

iwf_sink_rtc_id 16 Input Real Time Control ID of the eCPRI message.
Valid values are:
  • ID [7:0]: CPRI channel
  • ID [11:8]: 'h0- Ctrl_AxC, 'h1- Vendor Specific, 'h2- Real-time Vendor Specific

Valid on SOP assertion and stable until EOP assertion.

iwf_sink_msg_type 8 Input Indicate message type of the eCPRI message. IWF type 0 supports only message type 0 to 7 and 64-255 for eCPRI v1.2 specifications.

Valid on SOP assertion and stable until EOP assertion.

iwf_sink_reset_id 16 Input Indicate reset ID of the eCPRI message type 6. Lower byte maps to CPRI channel.

Valid on SOP assertion and stable until EOP assertion.

iwf_sink_reset_op 8 Input Indicate reset operation type of the eCPRI message type 6:
  • 8’b00000000- Remote Reset Request
  • 8’b00000001- Remote Reset Response
  • Others- Reserved

Valid on SOP assertion and stable until EOP assertion.

iwf_sink_event_type 8 Input Indicates event type of the eCPRI message type 7.

Valid on SOP assertion and stable until EOP assertion.

iwf_sink_event_id 8 Input Indicates event ID of the eCPRI message type 7. Lower byte maps to CPRI channel.

Valid on SOP assertion and stable until EOP assertion.

11 This is set to 64. This parameter is hidden from user and you can't change it.
Level Two Title