eCPRI Intel® FPGA IP User Guide

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ID 683685
Date 2/22/2024
Public
Document Table of Contents
Document Table of Contents x
1. Introduction 2. Getting Started 3. IP Parameters 4. Functional Description 5. Interface Overview 6. IP Registers 7. eCPRI Intel FPGA IP User Guide Archives 8. Document Revision History for eCPRI Intel® FPGA IP User Guide
1. Introduction x
1.1. Supported Features 1.2. Device Family Support 1.3. eCPRI Intel® FPGA IP Device Speed Grade Support 1.4. Resource Utilization 1.5. Intel® FPGA IP Core Verification 1.6. Release Information
2. Getting Started x
2.1. Installing and Licensing 2.2. Specifying the IP Core Parameters and Options 2.3. Generated File Structure 2.4. Simulating the IP Core 2.5. Compiling the Full Design and Programming the FPGA
2.2. Specifying the IP Core Parameters and Options x
2.2.1. Reference and System PLL Clock for your IP Design
4. Functional Description x
4.1. Interfaces 4.2. High Level Data Path Flow 4.3. Operation of the eCPRI IP Blocks
4.2. High Level Data Path Flow x
4.2.1. Transmit TX Path 4.2.2. Receive RX Path 4.2.3. Supported Ethernet Variants
4.3. Operation of the eCPRI IP Blocks x
4.3.1. Packet Classifier 4.3.2. Ethernet Header Insertion/Removal 4.3.3. Concatenation/De-concatenation 4.3.4. Header Mapper/De-Mapper 4.3.5. eCPRI IWF Type 0 4.3.6. eCPRI Message 5 Packet Parser 4.3.7. Packet Queue 4.3.8. eCPRI Message Type 4.3.9. Error Handling 4.3.10. RX Throttling
4.3.8. eCPRI Message Type x
4.3.8.1. eCPRI Message Type 0- IQ Data Transfer 4.3.8.2. eCPRI Message Type 1- Bit Sequence Transfer 4.3.8.3. eCPRI Message Type 2- Real Time Control Data 4.3.8.4. eCPRI Message Type 3- Generic Data Transfer 4.3.8.5. eCPRI Message Type 4- Remote Memory Access 4.3.8.6. eCPRI Message Type 5- One-Way Delay Measurement 4.3.8.7. eCPRI Message Type 6- Remote Reset 4.3.8.8. eCPRI Message Type 7- Event Indication 4.3.8.9. eCPRI Message Type 64- 255 Vendor Specific
5. Interface Overview x
5.1. Clock Signals 5.2. Power, Reset, and Firewalls Signals 5.3. TX Time of Day Interface 5.4. RX Time of Day Interface 5.5. Interrupt 5.6. Configuration Avalon® Memory-Mapped Interface 5.7. Ethernet MAC Source Interface 5.8. Ethernet MAC Sink Interface 5.9. External ST Source Interface 5.10. External ST Sink Interface 5.11. eCPRI IP Source Interface 5.12. eCPRI IP Sink Interface 5.13. Miscellaneous Interface Signals 5.14. IWF Type 0 eCPRI Interface 5.15. IWF Type 0 CPRI MAC Interface
5.2. Power, Reset, and Firewalls Signals x
5.2.1. Reset Control and Initialization Flows
5.7. Ethernet MAC Source Interface x
5.7.1. E-tile Hard IP for Ethernet 1588 PTP Signals 5.7.2. 25G Ethernet MAC 1588 PTP Signals 5.7.3. 10G Ethernet MAC 1588 PTP Signals
5.14. IWF Type 0 eCPRI Interface x
5.14.1. IWF Source Interface 5.14.2. IWF Sink Interface
5.15. IWF Type 0 CPRI MAC Interface x
5.15.1. CPRI 32-bit IQ Data TX Interface 5.15.2. CPRI 64-bit IQ Data TX Interface 5.15.3. CPRI 32-bit Ctrl_AxC TX Interface 5.15.4. CPRI 64-bit Ctrl_AxC TX Interface 5.15.5. CPRI 32-bit Vendor Specific TX Interface 5.15.6. CPRI 64-bit Vendor Specific TX Interface 5.15.7. CPRI 32-bit Real-time Vendor Specific TX Interface 5.15.8. CPRI 64-bit Real-time Vendor Specific TX Interface 5.15.9. CPRI Gigabit Media Independent Interface (GMII) 5.15.10. CPRI IP L1 Control and Status Interface
1. Introduction
2. Getting Started
3. IP Parameters
4. Functional Description
5. Interface Overview
6. IP Registers
7. eCPRI Intel FPGA IP User Guide Archives
8. Document Revision History for eCPRI Intel® FPGA IP User Guide

4.3.2. Ethernet Header Insertion/Removal

The Ethernet header insertion block inserts Ethernet header to incoming eCPRI packet on TX path. Optionally it can insert IPv4/UDP headers to the packet based on the configuration. The Ethernet header removal block removes Ethernet header to incoming eCPRI packet on RX path. Optionally it can remove IPv4/UDP headers to the packet based on the configuration selected. The Ethernet header encapsulated the incoming eCPRI packets as shown in the figure below. The table listed the source of each fields within the Ethernet header.
Figure 7. Ethernet Header Field
Table 15.  Ethernet Header Field and CSR
Ethernet Header Field CSR
Destination MAC address

Destination MAC address <N=0,1,2,3,4,5,6,7> Register 0,1

With enabled Advance mapping mode:

N – eCPRI message PCID [2:0]

Default mapping mode:

N = 0 for all eCPRI message
Source MAC address Source MAC address register 0, and 1
VLAN tag

VLAN Tag Register <N=0,1,2,3,4,5,6,7>

With Enabled advance mapping mode:

N – eCPRI message PCID [2:0]

Default mapping mode:

N = 0 for all eCPRI message
Ethertype 0xAEFE
eCPRI payload Incoming eCPRI packet from the eCPRI IP
If you select IPv4 header as encapsulation to eCPRI payload, the following table lists the CSR to fill the IPv4 header fields:
Table 16.  IPv4 Field and CSR
Number of Bits IPv4 Header CSR
48 (6 Bytes) MAC destination Address Refer to the Table: Ethernet Header Field and CSR above.
48 (6 Bytes) MAC source address Refer to the Table: Ethernet Header Field above.
16 (2 Bytes) Ethertype (2 Bytes)= IP 0x0800
4 Version ipv4_dw0_address
4 Internet header length ipv4_dw0_address
6 Differentiated Services Code Point (DSCP) ipv4_dw0_address
2 Explicit Congestion Notification (ECN) ipv4_dw0_address
16 Total length eCPRI IP calculates incoming IP packet header length
16 Identification ipv4_dw1_address
3 Flags ipv4_dw1_address
13 Fragment offset ipv4_dw1_address
8 Time to live ipv4_dw2_address
8 Protocol ipv4_dw2_address
16 Header checksum eCPRI IP calculates incoming IP packet header checksum
32 Source address ipv4_src_address_0
32 Destination address ipv4_dst_address_0
Table 17.  UDP Field and CSR
Number of Bytes IPv4 Header CSR
14 Ethernet header Refer to the Table: Ethernet Header Field and CSR above.
20 IPv4 header Refer to the Table: IPv4 Field and CSR Header above.
2 Source port mudp_dw0_address
2 Destination port mudp_dw0_address
2 Length eCPRI IP calculates incoming payload length
2 Checksum eCPRI IP calculates incoming payload checksum
Level Two Title