eCPRI Intel® FPGA IP User Guide

ID 683685
Date 2/22/2024
Public

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5.1. Clock Signals

Table 29.  eCPRI IP Input Clocks
Signal Name Width (Bits) I/O Direction Description
clk_tx 1 Input eCPRI IP TX clock.

For 25G eCPRI data rate variations, the default frequency value is 390.625 MHz.

For 10G eCPRI data rate variations, the default frequency value is 156.25 MHz.

clk_rx 1 Input eCPRI IP RX clock.

For 25G eCPRI data rate variations, the default frequency value is 390.625 MHz.

For 10G eCPRI data rate variations, the default frequency value is 156.25 MHz.

mac_clk_tx 1 Input Ethernet MAC TX clock.
The frequency of mac_clk_tx depends on device and data rate:
Device Data Rate mac_clk_tx Frequency(in )
Agilex™ 7 (E-tile) 25G 402.835 MHz
10G 161.32 MHz
Agilex™ 7 (F-tile) 25G 402.835 MHz
10G 161.32 MHz
Stratix® 10 (H-tile) 25G 390.625 MHz
10G 156.25 MHz
Stratix® 10 (E-tile) 25G 402.835 MHz
10G 161.32 MHz
Arria® 10 10G 156.25 MHz
mac_clk_rx 1 Input Ethernet MAC RX clock.
  • For the Stratix® 10 H-tile IP variations, the default frequency value is 390.625 MHz.
  • For the Stratix® 10 E-tile IP variations, the default frequency value is 402.835 MHz.
  • For the Agilex™ 7 E-tile and F-tile IP variations, the default frequency value is 402.835 MHz.
clk_csr 1 Input CSR clock. The default frequency value can be 100 MHz to 162 MHz.
ext_sink_clk 1 Input External user interface clock. The user needs to drive this clock at the same clock frequency configured at clk_tx.
cpri_clkout[N] 1 Input Master clock for the CPRI IP core.
The frequency of cpri_clkout[N] depends on the CPRI line bit rate:
CPRI Line Bit Rate cpri_clkout[N] Frequency
0.6144 Gbps 15.36 MHz
1.2288 Gbps 30.72 MHz
2.4576 Gbps 61.44 MHz
3.0720 Gbps 76.80 MHz
4.9152 Gbps 122.88 MHz
6.1440 Gbps 153.6 MHz
8.11008 Gbps 245.76 MHz
9.8304 Gbps 245.76 MHz
10.1376 Gbps 153.60 MHz1
307.20 MHz2
12.16512 Gbps 184.32 MHz
24.33024 Gbps 368.64 MHz
iwf_gmii_rxclk[N] 1 Input iwf_gmii_txclk clocks the GMII transmitter interface and iwf_gmii_rxclk clocks the GMII receiver interface. You must drive these clocks at the frequency of 125 MHz to achieve the 1000 Mbps bandwidth required for this interface.

These clocks are present only if you set the value of Ethernet PCS interface to the value of GMII in the CPRI parameter editor.

iwf_gmii_txclk[N] 1 Input
gmii_rxclk[N] 1 Output gmii_txclk clocks the GMII transmitter interface and gmii_rxclk clocks the GMII receiver interface. You must drive these clocks at the frequency of 125 MHz to achieve the 1000 Mbps bandwidth required for this interface.

These clocks are present only if you set the value of Ethernet PCS interface to the value of GMII in the CPRI parameter editor.

gmii_txclk[N] 1 Output
1 For Agilex™ 7 E-tile and F-tile and Stratix® 10 E-tile device variations.
2 For all other device variations.