L-Tile and H-Tile Avalon® Memory-mapped Intel® FPGA IP for PCI Express* User Guide

ID 683667
Date 9/13/2024
Public
Document Table of Contents

2.5. Simulating the Design Example

Figure 17. Procedure
  1. Change to the testbench simulation directory, pcie_example_design_tb.
  2. Run the simulation script for the simulator of your choice. Refer to the table below.
  3. Analyze the results.
Table 9.  Steps to Run Simulation
Simulator Working Directory Instructions
Questa Intel FPGA Edition <example_design>/pcie_example_design_tb/pcie_example_design_tb/sim/mentor/
  1. Invoke vsim (by typing vsim, which brings up a console window where you can run the following commands).
  2. do msim_setup.tcl
    Note: Alternatively, instead of doing Steps 1 and 2, you can type: vsim -c -do msim_setup.tcl.
  3. ld_debug
  4. run -all
  5. A successful simulation ends with the following message, "Simulation stopped due to successful completion!"
ModelSim* <example_design>/pcie_example_design_tb/pcie_example_design_tb/sim/mentor/
  1. Invoke vsim (by typing vsim, which brings up a console window where you can run the following commands).
  2. do msim_setup.tcl
    Note: Alternatively, instead of doing Steps 1 and 2, you can type: vsim -c -do msim_setup.tcl.
  3. ld_debug
  4. run -all
  5. A successful simulation ends with the following message, "Simulation stopped due to successful completion!"
VCS* <example_design>/pcie_example_design_tb/pcie_example_design_tb/sim/synopsys/vcs
  1. sh vcs_setup.sh USER_DEFINED_COMPILE_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="-xlrm\ uniq_prior_final" USER_DEFINED_SIM_OPTIONS=""
  2. A successful simulation ends with the following message, "Simulation stopped due to successful completion!"
NCSim* <example_design>/pcie_example_design_tb/pcie_example_design_tb/sim/cadence
  1. sh ncsim_setup.sh USER_DEFINED_SIM_OPTIONS="" USER_DEFINED_ELAB_OPTIONS="-timescale\ 1ns/1ps"
  2. A successful simulation ends with the following message, "Simulation stopped due to successful completion!"
Xcelium* Parallel Simulator <example_design>/pcie_example_design_tb/pcie_example_design_tb/sim/xcelium
  1. sh xcelium_setup.sh USER_DEFINED_SIM_OPTIONS="" USER_DEFINED_ELAB_OPTIONS ="-timescale\ 1ns/1ps\ -NOWARN\ CSINFI"
  2. A successful simulation ends with the following message, "Simulation stopped due to successful completion!"
The DMA testbench completes the following tasks:
  1. Writes to the Endpoint memory using the DUT Endpoint non-bursting Avalon® -MM master interface.
  2. Reads from Endpoint memory using the DUT Endpoint non-bursting Avalon® -MM master interface.
  3. Verifies the data using the shmem_chk_ok task.
  4. Writes to the Endpoint DMA controller, instructing the DMA controller to perform a MRd request to the PCIe* address space in host memory.
  5. Writes to the Endpoint DMA controller, instructing the DMA controller to perform a MWr request to PCIe* address space in host memory. This MWr uses the data from the previous MRd.
  6. Verifies the data using the shmem_chk_ok task.

The simulation reports, "Simulation stopped due to successful completion" if no errors occur.

Figure 18. Partial Transcript from Successful Simulation Testbench