AN 848: Implementing Intel® Cyclone® 10 GX Triple-Rate SDI II with Nextera FMC Daughter Card Reference Design

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Date 7/05/2018
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Document Table of Contents x
AN 848: Implementing Intel® Cyclone® 10 GX Triple-Rate SDI II with Nextera FMC Daughter Card Reference Design
AN 848: Implementing Intel® Cyclone® 10 GX Triple-Rate SDI II with Nextera FMC Daughter Card Reference Design x
Reference Design Block Diagram Key Features Design Components Requirements Reference Design Walkthrough Document Revision History for AN 848: Implementing Intel® Cyclone® 10 GX Triple-Rate SDI II with Nextera FMC Daughter Card Reference Design
Requirements x
Hardware Requirements Software Requirements
Reference Design Walkthrough x
Running the Reference Design Customizing the Intel® Quartus® Prime Pro Edition Reference Design Viewing the Results
Running the Reference Design x
Compiling the Project Setting up the Hardware Configuring the FPGA Checking the Video Formats and Jitter Reading
Customizing the Intel® Quartus® Prime Pro Edition Reference Design x
Generating the Reference Design Customizing the Reference Design
Viewing the Results x
Monitor User LEDs Verify the Video Image and Jitter Results at the Signal Analyzer
AN 848: Implementing Intel® Cyclone® 10 GX Triple-Rate SDI II with Nextera FMC Daughter Card Reference Design

Monitor User LEDs

Figure 6. User LEDs

This test uses the following LEDs to indicate the respective conditions.

Table 4.  User LEDsThe User LEDs indicate the expected results. A logical 1 indicates that the LED illuminates and a logical 0 indicates otherwise.
User LEDs Results
PB0 = ON PB0 = OFF
D19

The standard of the RX signal video:

  • SD: [D21, D20, D19] = 000
  • HD: [D21, D20, D19] = 001
  • 3Gb: [D21, D20, D19] = 010
  • 3Ga: [D21, D20, D19] = 011
 Illuminates when the frame_locked signal is asserted.
D20 Illuminates when the trs_locked signal is asserted.
D21 Illuminates when the aligned_locked signal is asserted.
Level Two Title