AN 848: Implementing Intel® Cyclone® 10 GX Triple-Rate SDI II with Nextera FMC Daughter Card Reference Design

ID 683643
Date 7/05/2018
Public

Customizing the Reference Design

In the Intel® Quartus® Prime Pro Edition software, follow these steps:

  1. Assume your design uses a 125-MHz clock for both the TX and RX Avalon® -MM interfaces for the reconfiguration and PHY reset controller blocks. Follow these steps to change the clock from 100 MHz to 125 MHz.
    1. Change the explicit clock rate for the following Clock Bridge components to 125000000.
      reconfig_clk and rx_phy_rst_ctrl_clk (located in the sdi_rx_sys.qsys)
      tx_phy_rst_ctrl_clk (located in the sdi_tx_sys.qsys)
    2. Change the input clock frequency for the TX and RX Transceiver PHY Reset Controller Intel® FPGA IP to 125 MHz. The related components are:
      rx_phy_rst_ctrl (located in the sdi_rx_sys.qsys)
      tx_phy_rst_ctrl (located in the sdi_tx_sys.qsys)
      Note: You must double click on each component to open it in the parameter editor before you can change the value. You can skip this step if you use a 100-MHz clock for both the TX and RX Avalon® -MM interfaces for the reconfiguration and PHY reset controller blocks.
  2. The reference design uses a 297-MHz TX PLL reference clock. Follow these steps to change the TX PLL reference clock.
    1. Open the tx_pll.ip (located at /rtl/tx/ directory).
    2. Change the PLL reference clock frequency to 297 MHz.
    3. Click Generate HDL button and then Generate button to generate the HDL design files for synthesis.
  3. The {usb_refclk_p} is renamed to {fmc_gbtclk_m2c_p0} in the top-level file of this reference design. The {c10_refclk_2_p} is renamed to {c10_refclk_1_p} in the top-level file of this reference design.
  4. Update the clock constraints in sdi_ii_c10_demo.sdc:
    1. Remove the following:
      create_clock -period "100 MHz" -name{c10_refclk_2_p}{c10_refclk_2_p}
      create_clock -period "148.5 MHz" -name{usb_refclk_p}{usb_refclk_p}
    2. Add the following:
      create_clock -period "125 MHz" -name {c10_refclk_1_p}{c10_refclk_1_p}
      create_clock -period "297 MHz" -name {fmc_gbtclk_m2c_p0}{fmc_gbtclk_m2c_p0}
  5. The reference design generated is not targeted on any development kit. You will need to manually assign your pin assignments. The following are the example pin assignments used in the reference design created using the Intel® Cyclone® 10 GX Development Kit.
    Table 3.  Reference Design Pin Assignments for Intel® Cyclone® 10 GX Development Kit
    Signal Direction Pin Location Description
    c10_refclk_1_p Input PIN_AB16 125-MHz clock for reconfiguration in the Avalon® -MM interfaces.
    sfp_refclk_p Input PIN U24 RX transceiver reference clock and SDI RX core clock.
    fmc_gbtclk_m2c_p0 Input PIN_W24 297-MHz TX PLL reference clock from the Nextera daughter card.
    user_pb [0] Input PIN_AE4 Push button for the LEDs to switch between displaying the rx_std or rx_lock status.
    user_pb [1] Input PIN_AD4 Push button to power down LMK03328 after switching the jumper settings.
    user_pb [2] Input PIN_AH2 Push button for global reset.
    user_led[3..0] Output PIN_AC7, PIN_AC6, PIN_AE6, PIN_AF6 Green LED display.
    fmc_dp_m2c_p2 Input PIN_AB26 SDI RX serial data from the FMC port.
    fmc_la_tx_p1 Input PIN_L1 RX cable equalizer lock status on the Nextera daughter card.
    fmc_dp_c2m_p0 Output PIN_AG28 SDI TX serial data from the FMC port.
    fmc_la_tx_p12 Output PIN_W4 Initialize LMH1983 on the Nextera daughter card.
    fmc_la_tx_n12 Output PIN_Y4 F-sync signal for LMH1983 on the Nextera daughter card.
    fmc_la_tx_p14 Output PIN_T4 V-sync signal for LMH1983 on the Nextera daughter card.
    fmc_la_tx_n14 Output PIN_U5 H-sync signal for LMH1983 on the Nextera daughter card.
    fmc_la_tx_p15 Output PIN_U6 Power-down signal for LMH1983 on the Nextera daughter card.

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