AN 848: Implementing Intel® Cyclone® 10 GX Triple-Rate SDI II with Nextera FMC Daughter Card Reference Design

ID 683643
Date 7/05/2018

Generating the Reference Design

Follow these steps to generate the reference design:

  1. Launch the Intel® Quartus® Prime Pro Edition software.
  2. Create a project and select your Intel® Cyclone® 10 GX device.
  3. In the IP Catalog, select SDI II Intel® FPGA IP . The New IP Variant window appears.
  4. Specify a top-level name for your custom IP variation. The parameter editor saves the IP variation settings in a file named <your_ip>.ip.
  5. Click Create. The parameter editor appears.
  6. On the IP tab, select the following settings:
    1. Select Triple rate (up to 3G-SDI) for the video standard option.
    2. Select Transmitter or Receiver for the direction option.
  7. On the Design Example tab, select the following settings:
    1. Select Parallel loopback with external VCXO for the select design option.
    2. Select CMU/fPLL for the TX PLL type option.
    3. Select Synthesis checkbox for the design example files option.
    4. Select Verilog for the generate file format option.
    5. Select Custom Development Kit for the select board option.
  8. Click Generate Example Design.