AN 502: Implementing SMBus Controller in Altera MAX Series

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ID 683635
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. Implementing SMBus Controller in Altera MAX Series
1. Implementing SMBus Controller in Altera MAX Series x
1.1. Using a MAX II Device as an SMBus Controller 1.2. Acknowledgments 1.3. Document Revision History
1.1. Using a MAX II Device as an SMBus Controller x
1.1.1. Data Transfer on SMBus 1.1.2. Host Interface 1.1.3. Communicating with the SMBus Controller
1.1.2. Host Interface x
1.1.2.1. Interface Signals 1.1.2.2. Registers 1.1.2.3. Address Register 1.1.2.4. Data Register 1.1.2.5. Status Register
1.1.3. Communicating with the SMBus Controller x
1.1.3.1. Using the Status Register 1.1.3.2. IRQ Signal 1.1.3.3. BUSY Signal
1. Implementing SMBus Controller in Altera MAX Series

1.1.2.5. Status Register

The status register contains the status information of the ongoing process.
Table 5.  Status Register BitsThe status register is cleared if a STOP is generated by the controller. Only the bits 4 to 0 in the status register are written by the host. The value on the remaining bits should not be changed by the host. All the registers can be read and/or written.
Bit Name Description
Set Cleared
7 AM By the SMBus controller when Address matches in slave mode By the SMBus controller after the operation to be carried in the slave mode is completed
6 DTE By the SMBus controller if data cannot be transferred only in slave mode By the host before the next Master/Slave operation
5 AL Arbitration was lost Normal operation
4 M/S SMBus controller is functioning as a master SMBus controller is functioning as a slave
3 R/W Forces the SMBus controller to read data from SMBDAT "Forces the SMBus controller to write data onSMBDAT"
2 PEC "Only in the master mode if the slave isPEC enabled" By the microcontroller
1 STOP Generates a stop condition Normal operation
0 START Generates a start condition Normal operation
Level Two Title