AN 502: Implementing SMBus Controller in Altera MAX Series

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ID 683635
Date 9/22/2014
Public

1.1.2.5. Status Register

The status register contains the status information of the ongoing process.
Table 5.  Status Register BitsThe status register is cleared if a STOP is generated by the controller. Only the bits 4 to 0 in the status register are written by the host. The value on the remaining bits should not be changed by the host. All the registers can be read and/or written.
Bit Name Description
Set Cleared
7 AM By the SMBus controller when Address matches in slave mode By the SMBus controller after the operation to be carried in the slave mode is completed
6 DTE By the SMBus controller if data cannot be transferred only in slave mode By the host before the next Master/Slave operation
5 AL Arbitration was lost Normal operation
4 M/S SMBus controller is functioning as a master SMBus controller is functioning as a slave
3 R/W Forces the SMBus controller to read data from SMBDAT "Forces the SMBus controller to write data onSMBDAT"
2 PEC "Only in the master mode if the slave isPEC enabled" By the microcontroller
1 STOP Generates a stop condition Normal operation
0 START Generates a start condition Normal operation
Level Two Title