AN 502: Implementing SMBus Controller in Altera MAX Series

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ID 683635
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. Implementing SMBus Controller in Altera MAX Series
1. Implementing SMBus Controller in Altera MAX Series x
1.1. Using a MAX II Device as an SMBus Controller 1.2. Acknowledgments 1.3. Document Revision History
1.1. Using a MAX II Device as an SMBus Controller x
1.1.1. Data Transfer on SMBus 1.1.2. Host Interface 1.1.3. Communicating with the SMBus Controller
1.1.2. Host Interface x
1.1.2.1. Interface Signals 1.1.2.2. Registers 1.1.2.3. Address Register 1.1.2.4. Data Register 1.1.2.5. Status Register
1.1.3. Communicating with the SMBus Controller x
1.1.3.1. Using the Status Register 1.1.3.2. IRQ Signal 1.1.3.3. BUSY Signal
1. Implementing SMBus Controller in Altera MAX Series

1.1.3.1. Using the Status Register

If the host wants to configure the controller in Master mode to perform a read operation with the CRC checking enabled:

  1. The host sets the START, PEC, R/W, and M/S bits of the status register. The first byte of data that is transferred on the bus (address of the slave to be communicated) is written in the data register.
  2. The controller then serially outputs the data on the SMBDAT line.
  3. After the controller receives an acknowledgement, the controller reads a byte of data and interrupts the host, which should now read the data from the data register.
  4. If the host is not reading the data from the data register, the controller waits for approximately 32 ms and sets the IRQ and the busy_bus signals.
  5. If the host wants the controller to generate a stop condition after reading a byte of data, the host sets the STOP bit in the status register. The STOP bit is generated after reading two bytes if the PEC bit is set. If the PEC bit is not set, the STOP bit is generated after reading only one byte of data.
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