AN 502: Implementing SMBus Controller in Altera MAX Series

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ID 683635
Date 9/22/2014
Public
Document Table of Contents
Document Table of Contents x
1. Implementing SMBus Controller in Altera MAX Series
1. Implementing SMBus Controller in Altera MAX Series x
1.1. Using a MAX II Device as an SMBus Controller 1.2. Acknowledgments 1.3. Document Revision History
1.1. Using a MAX II Device as an SMBus Controller x
1.1.1. Data Transfer on SMBus 1.1.2. Host Interface 1.1.3. Communicating with the SMBus Controller
1.1.2. Host Interface x
1.1.2.1. Interface Signals 1.1.2.2. Registers 1.1.2.3. Address Register 1.1.2.4. Data Register 1.1.2.5. Status Register
1.1.3. Communicating with the SMBus Controller x
1.1.3.1. Using the Status Register 1.1.3.2. IRQ Signal 1.1.3.3. BUSY Signal
1. Implementing SMBus Controller in Altera MAX Series

1.1.2.3. Address Register

The address register is an 8-bit register and stores the address of the slave module of the controller.
Table 3.  Address RegisterYou can use the LSB to enable or disable the controller and the remaining 7 bits as the address of the controller. If the LSB is set, the controller is enabled. Clearing it forces the controller to not respond when it detects that its address is being sent on the bus.
Bit Name Description
7..1 Slave Address Address of the controller (in slave mode)
0 Enable/Disable If set, enables the controller
Level Two Title