AN 502: Implementing SMBus Controller in Altera MAX Series

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ID 683635
Date 9/22/2014
Public

1.1.2.1. Interface Signals

The SMBus controller uses an asynchronous interface consisting of the signals shown in the following table.
Table 1.  Asynchronous Interface Signals for SMBus Controller All the signals are active high except CS, which is active low. When it is high, all the other lines become tri-stated except Interrupt Request (IRQ).
Signal Connection Description
ADDRESS BUS [8] Input μC address bus used to select the desired register.
DATA BUS [8] Bidir μC data bus.
IRQ Output Interrupt request.
BUSY Output Indicates whether the bus is idle or busy.
CS Input Chip Select.
RD Input Places the data of the selected register on the data bus.
WR Input Writes the data present on the data bus to the selected register.
RESET Input Resets the controller.
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